3.2 Optional Load Transient Input/Output Connector Descriptions
3.2.1 VDD and GND
VDD and GND are the connection terminals for the input supply of the load transient circuit. The VDD terminal is
the positive connection, and the GND terminal is the negative (that is, ground) connection.
3.2.2 J15
J15 is an optional connection for the user to make measurements or apply loads to the output of the LDO.
3.2.3 J18
J18 is an optional connection to insert a damping circuit across the load transient MOSFET drain to source
voltage.
3.2.4 J19
J19 is an optional connection to insert capacitance or additional load across the drain to source of the load
transient MOSFET.
3.2.5 J21
J21 is the connection for the function generator to drive the gate driver device. J21 is terminated by the 50-Ω
resistor, R21.
3.2.6 J22
J22 is a high-frequency kelvin connection that allows accurate measurements of the load transient MOSFET
drain to source voltage.
3.2.7 J23
Short J23 to enable the gate driver.
3.2.8 J26
J26 is a high-frequency kelvin connection that allows accurate measurements of the load transient MOSFET
gate to source voltage.
3.2.9 TP3
TP3 is the test point used to enable the gate driver device. Tie this pin to GND to enable the gate driver.
3.3 TPS7B4255-Q1 LDO Operation and Component Selection
The TPS7B4255EVM-062 evaluation module contains the TPS7B4255-Q1 LDO with input and output capacitors
installed. These three components provide an implementation example, as illustrated by the white boxes
in
. The prepopulated capacitors are sized to ensure the minimum capacitance requirements are
maintained under all normal operating conditions. Optional pads are available to test the LDO with additional
setpoint options, as well as input and output capacitors beyond what is already installed on the EVM.
Setpoint resistors are prepopulated on the TPS7B4255EVM-062 to configure the TPS7B84-Q1 LDO with an
output voltage of 3.3 V, 5 V, or 8 V. With a shunt placed across the pins of jumper J11, the output of the
TPS7B84-Q1 supplies the ADJ/EN pin of the TPS7B4255-Q1. If a different voltage than the TPS7B84-Q1 output
is desired to drive the ADJ/EN pin, remove the shunt from jumper J11 and use a combination of J5, R1, R3, and
C10 to configure the ADJ/EN pin to be a function of the input voltage. Alternatively, TP1 can be used to directly
drive ADJ/EN with an external voltage source.
The TPS7B84-Q1 LDO can be enabled or disabled by using the J14 3-pin header:
• Place a 2-pin shunt across the header to tie VIN to EN to enable the device
• Place a 2-pin shunt across the header to tie GND to EN to disable the device
Alternatively, by connecting an external function generator to TP2 (EN) and a nearby GND post (J9), the
user can enable or disable the TPS7B84-Q1 LDO after VIN is applied.
TPS7B4255EVM-062 during turn-on. Jumper J14 has a shunt to connect EN of the TPS7B84-Q1 to VIN to
enable the device for this turn-on plot.
Setup
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TPS7B4255EVM-062 Evaluation Module
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