ADS1282-SP EVM Detailed Description
16
SBAU274 – July 2016
Copyright © 2016, Texas Instruments Incorporated
ADS1282-SP Evaluation Module (ADS1282EVM-CVAL)
Table 2. ADS1282-SP EVM Test Points Description (continued)
Test Point
Silk Screen
Schematic Page
Description
TP23
VCCM1
Analog
Common Mode Node of Channel 1
TP24
AUX_REFP
Analog
ADC REFP from J10
TP25
VOCM
Analog
REF5025 2.5-V Output
TP26
ADC_CLK
ADC
External Clock to ADC
TP27
GND
ADC
Global Ground Plane
5.6
ADS1282-SP EVM Layout
The device distinguishes between two different grounds: AVSS (analog ground) and DGND (digital
ground). In low-frequency applications such as temperature sensing with thermocouples, laying out the
printed circuit board (PCB) to use a single ground plane is adequate but care must be taken so that
ground loops are avoided. Ground loops act as loop antennas picking up interference currents which
transform into voltage fluctuations. These fluctuations are effectively noise which can degrade system
performance in high-resolution applications. When placing components and routing over the ground plane,
pay close attention to the path that ground currents will take. Avoid having return currents for digital
functions pass close to analog-sensitive devices or traces.
Additionally, the proximity of digital devices to an analog signal chain has the potential to induce unwanted
noise into the system. One primary source of noise is the switching noise from any digital circuitry such as
the data output serializer or the microprocessor receiving the data. For the device, care must be taken to
ensure that the interaction between the analog and digital supplies within the device is kept to a minimal
amount. The extent of noise coupled and transmitted from the digital and analog sections depends on the
effective inductances of each of the supply and ground connections. Smaller effective inductances of the
supply and ground pins results in better noise suppression. For this reason, multiple pins are used to
connect to the digital ground. Low inductance properties must be maintained throughout the design of the
PCB layout by use of proper planes and layer thickness.
To avoid noise coupling through supply pins, TI recommends to keep sensitive input pins (such as AINN1,
AINP1, AINN2, and AINP2) away from the DVDD and DGND planes. For example, do not route the traces
or vias connected to these pins across these planes; that is, avoid the digital power planes under the
analog input pins. An exception may be acceptable to share DGND and AVSS when utilizing a unipolar
supply for AVDD. As in the example below, DGND is shared with AVSS. Care should be taken to
minimize inductance and route digital signals away from the analog section. The analog inputs represent
the most sensitive node of the ADC as the total system accuracy depends on how well the integrity of this
signal is maintained. The analog differential inputs to the ADC should be routed tightly-coupled and
symmetrical for common mode rejection. These inputs should be as short in length as possible, to
minimize exposure to potential sources of noise.