Texas Instruments TPS6594-Q1 Series, User Manual

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EVM Details
9 SLVUBT0 – December 2019
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TPS6594x-Q1 Evaluation Module
Table 8. Header J8 Pullup Voltages
J8, Pin(s) Pullup Voltage Description
1,2,7-11 VIO_IN GPIO1,GPIO2, GPIO7-11: Output Type
Selection; Power Domain is VIO
3,4 VOUT_LDOVRTC GPIO3 and GPIO4: Input Type Selection;
Power Domain is VRTC
5,6 VOUT_LDOVINT GPIO5 and GPIO6: Output Type
Selection; Power Domain is VINT
3.5 Stack-up Headers
As shown in , multiple boards can be configured into a master-slave relationship (1 master and up to 5
slaves) and physically stacked upon each other. VCCA and GND are shared between boards on headers
J27 and J28. Communication between the boards is shared on header J29. This header, J29, is marked
on the bottom silkscreen, as shown in
Figure 5 .
Figure 4. EVM Masters Slave Configuration