Board Layout
8
SLUUC02 – February 2019
Copyright © 2019, Texas Instruments Incorporated
TPS65295EVM-079, 4.5-V to 18-V
IN
, complete DDR4 power solution
evaluation module
4
Board Layout
This section provides a description of the TPS65295EVM-079 board layout and layer illustrations.
This section provides a description of the TPS65295EVM-079 board layout and layer illustrations. The
board layout for the TPS65295EVM-079 is shown in Figure 9 ~ Figure 12. The top and bottom are 2-oz.
copper and internal layers are 1-oz. copper.
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Place the decoupling capacitors right across PVIN, PVIN_VPP, and VLDOIN as close as possible.
•
Place output inductors and capacitors with IC at the same layer, SW routing should be as short as
possible to minimize EMI, and should be a width plane to carry big current, enough vias should be
added to the PGND connection of output capacitor and also as close to the output pin as possible.
Reserve some space between VDDQ choke and VPP choke, just minimize radiation crosstalk.
•
Place BST resistor and capacitor with IC at the same layer, close to BST and SW plane, >15mil width
trace is recommended to reduce line parasitic inductance.
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VPPSNS/VDDQSNS/VTTSNS could be 10mil and must be routed away from the switching node, BST
node or other high efficiency signal.
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PVIN and PVIN_VPP trace must be wide to reduce the trace impedance and provide enough current
capability.
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Output capacitors for VTT and VTTREF should be put as close as output pin.
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For the TPS65295, an additional input bulk capacitor may be required, depending on the EVM
connection to the input supply.
Figure 8. Top Assembly