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Table 1-2. TPS5430EVM-173 and TPS5431EVM-173 Performance Specification Summary (continued)

SPECIFICATION

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Loop bandwidth

TPS5430EVM-173

VIN = 25 V, I

O

 = 1 A

25.0

kHz

TPS5431EVM-173

VIN = 15 V, I

O

 = 1 A

23.9

Phase margin

TPS5430EVM-173

VIN = 25 V , I

O

 = 1 A

50°

TPS5431EVM-173

VIN = 15 V, I

O

 = 1 A

51°

Input ripple voltage

TPS5430EVM-173

I

O

 = 3 A

255

300

mVpp

TPS5431EVM-173

295

350

Output ripple voltage

TPS5430EVM-173

I

O

 = 3 A

20

mVpp

TPS5431EVM-173

20

Output rise time

8

ms

Operating frequency

500

kHz

Max efficiency

TPS5430EVM-173

VIN = 10 V, V

O

 = 5 V, I

O

 = 0.75 A

93.6%

TPS5431EVM-173

VIN = 9 V, V

O

 = 5 V, I

O

 = 0.75 A

94.0%

1.3 Modifications

These evaluation modules are designed to demonstrate the small size that can be attained when designing with 
the TPS5430 and TPS5431. A few changes can be made to this module.

1.3.1 Output Voltage Set Point

To change the output voltage of the EVMs, it is necessary to change the value of resistor R2. Changing the 
value of R2 can change the output voltage above 1.25 V. The value of R2 for a specific output voltage can be 
calculated using 

Equation 1

.

R2

+

10 k

W

 

1.221 V

V

O

*

1.221 V

(1)

Table 1-3

 lists the R2 values for some common output voltages. Note that VIN must be in a range so that the 

minimum on-time is greater than 200 ns, and the maximum duty cycle is less than 87%. The values given in 

Table 1-3

 are standard values, not the exact value calculated using 

Equation 1

.

Table 1-3. Output Voltages Available

Output Voltage (V)

R

2

 Value (kΩ)

1.8

21.5

2.5

9.53

3.3

5.90

5

3.24

2 Test Setup and Results

This section describes how to properly connect, set up, and use the TPS5430EVM-173 and TPS5431EVM-173 
evaluation modules. The section also includes test results typical for the evaluation modules and covers 
efficiency, output voltage regulation, load transients, loop response, output ripple, input ripple, and startup.

2.1 Input/Output Connections

The TPS5430EVM-173 and TPS5431EVM-173 are provided with input/output connectors and test points as 
shown in 

Table 2-1

. A power supply capable of supplying 3 A must be connected to J1 through a pair of 20 AWG 

wires. The load must be connected to J3 through a pair of 20 AWG wires. The maximum load current capability 
should be 3 A. Wire lengths must be minimized to reduce losses in the wires. Test-point TP1 provides a place 
to monitor the VIN input voltages with TP2 providing a convenient ground reference. TP3 is used to monitor the 
output voltage with TP4 as the ground reference.

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Introduction

SLVU157A – MARCH 2006 – REVISED OCTOBER 2021

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TPS5430 and TPS5431 Step-Down Converter Evaluation Module User's 

Guide

3

Copyright © 2021 Texas Instruments Incorporated

Summary of Contents for TPS5430

Page 1: ...S5431 Line Regulation 7 Figure 2 7 PS5430 Transient Response 7 Figure 2 8 TPS5431 Transient Response 8 Figure 2 9 TPS5430 Loop Response 8 Figure 2 10 PS5431 Loop Response 9 Figure 2 11 TPS5430 Output...

Page 2: ...5430 31 provides an enable input The absolute maximum input voltage is 38 V for the TPS5430EVM 173 and 25 V for the TPS5431EVM 173 Table 1 1 Input Voltage and Output Current Summary EVM INPUT VOLTAGE...

Page 3: ...on time is greater than 200 ns and the maximum duty cycle is less than 87 The values given in Table 1 3 are standard values not the exact value calculated using Equation 1 Table 1 3 Output Voltages A...

Page 4: ...VMs peak at a load current of about 0 75 A and then decrease as the load current increases towards full load Figure 2 1 shows the efficiency for the TPS5430EVM 173 at an ambient temperature of 25 C 75...

Page 5: ...ut Voltage Load Regulation The load regulation for the TPS5430EVM 173 and TPS5431EVM 173 are shown in Figure 2 3 and Figure 2 4 0 1 0 08 0 06 0 04 0 02 0 0 02 0 04 0 06 0 08 0 1 0 0 5 1 1 5 2 2 5 3 I...

Page 6: ...the TPS5430EVM 173 and TPS54310EVM 173 are shown in Figure 2 5 and Figure 2 6 0 1 0 08 0 06 0 04 0 02 0 0 02 0 04 0 06 0 08 0 1 10 15 20 25 30 35 I 0 A O I 1 5 A O I 3 A O V Input Voltage V I Output R...

Page 7: ...wn in Figure 2 7 and Figure 2 8 The current step is from 25 to 75 of maximum rated load Total peak to peak voltage variation is as shown including ripple and noise on the output V 50 mV Div AC Coupled...

Page 8: ...are shown for VIN voltage of 25 V for the TPS5430EVM 173 and 15 V for the TPS5431EVM 173 Load current for both measurements is 1 A 60 60 100 1 M 180 180 Gain dB f Frequency Hz Phase deg Gain Phase Fig...

Page 9: ...re 2 12 The output current is the rated full load of 3 A Voltage is measured directly across output capacitors Time 1 s Div V 20 mV Div AC Coupled OUT V 20 V Div P Figure 2 11 TPS5430 Output Ripple ww...

Page 10: ...13 and Figure 2 14 The output current for each device is at full rated load of 3 A Time 1 s Div V 20 V Div PH V 100 mV Div AC Coupled IN Figure 2 13 TPS5430 Input Ripple Test Setup and Results www ti...

Page 11: ...1 06 V the start up sequence begins and the internal reference voltage begins to ramp up at the internally set rate towards 1 221 V and the output voltage ramps up to the externally set value of 5 V T...

Page 12: ...ENA feature The top and bottom and internal ground traces are connected with multiple vias placed around the board including four vias directly under the TPS5430 device to provide a thermal path from...

Page 13: ...p Side Figure 3 3 Top Side Assembly www ti com Board Layout SLVU157A MARCH 2006 REVISED OCTOBER 2021 Submit Document Feedback TPS5430 and TPS5431 Step Down Converter Evaluation Module User s Guide 13...

Page 14: ...ection 4 1 Schematic The schematic for the TPS5430EVM 173 and TPS5431EVM 173is shown in Figure 4 1 Schematic and Bill of Materials www ti com 14 TPS5430 and TPS5431 Step Down Converter Evaluation Modu...

Page 15: ...tic www ti com Schematic and Bill of Materials SLVU157A MARCH 2006 REVISED OCTOBER 2021 Submit Document Feedback TPS5430 and TPS5431 Step Down Converter Evaluation Module User s Guide 15 Copyright 202...

Page 16: ...1 1 R1 10 0k Resistor Chip 1 16W 1 0603 Std Std 1 1 R2 3 24k Resistor Chip 1 16W 1 0603 Std Std 1 1 R3 0 Resistor Chip 1 16W 1 0603 Std Std 4 4 TP1 TP3 TP5 TP6 Test Point Red Thru Hole Color Keyed 0 1...

Page 17: ...ther than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control tec...

Page 18: ...These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not in...

Page 19: ...instructions set forth by Radio Law of Japan which includes but is not limited to the instructions below with respect to EVMs which for the avoidance of doubt are stated strictly for convenience and s...

Page 20: ...any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electr...

Page 21: ...R DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthe...

Page 22: ...change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of thes...

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