Description
3
Description
TPS2379EVM-106 enables full evaluation of the TPS2379 device. Refer to the schematic shown in
. Ethernet power is applied from J1 to T1/T2 and is dropped to the diode bridges (D3/D4/D8/D9 or
D5/D6/D10/D11) from the T1/T2 center taps. The series R-C circuit from each center tap help balance the
Ethernet cable impedance and are critical for ESD and EMI/EMC performance. These circuits are
terminated at TP10 (EGND) through the high voltage capacitor, C9. At the output of the diode bridges is
the EMI/EMC filter and transient protection for the TPS2379. R7 provides the detection signature and R8
provides the class 4 signature resistance to the PSE. A shunt on J6 can be installed to present a 12.5k
Ω
detection signature resistance. A shunt on J7 can be installed to present a 37.4
Ω
(68mA) class signature
resistance.
To the right of the TPS2379 (U1) is the switched side of the PD controller. The TPS2379 RTN pin
provides inrush limited turn on and charge of the bulk capacitor, C3. During inrush, the TPS2379 GATE
pin is pulled low (with respect to VSS) disabling the external boost MOSFET, Q2. When inrush is
complete, the GATE pin goes high and enables a parallel conduction path through Q2 and the TPS2379
internal MOSFET. Q1 provides current limit for the external MOSFET when the voltage between TP12 and
TP11 reaches the base-emitter on threshold of Q1.
Additionally during inrush, the TPS2379 CDB pin is pulled low (with respect to the RTN pin). Since the
CDB pin is connected to the GATE of Q3, Q3 is off during inrush and J4 pin 1 is not connected to the RTN
pin. This allows the output load to remain connected during EVM testing. LED’s D1 and D2 provide
operational visual indications of T2P and ON respectively.
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SLVU687 – March 2012
TPS2379 EVM User’s Guide
Copyright © 2012, Texas Instruments Incorporated
