Module Operation
392
SPNU563A – March 2018
Copyright © 2018, Texas Instruments Incorporated
Level 2 RAM (L2RAMW) Module
8.2.3 L2RAMW Auto-Initialization
The RAM memory can be initialized by using the dedicated auto-initialization hardware. The L2RAMW
module initializes the entire memory when the auto-init is enabled for the RAM. All RAM data memory is
initialized to zeros and the ECC memory is initialized to the correct ECC value for zeros, that is, 0Ch.
8.2.4 Trace Module Support
The L2RAMW module traces out the following signals to the RAM Trace Port (RTP) module, thereby
providing RAM dataport trace capability.
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18-bit address line
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64-bit data bus
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Byte strobe information
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Current access master identification number
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Access type: Opcode or data fetch
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Read or Write access
No data is traced for an access to ECC memory.
8.2.5 Emulation/Debug Mode Behavior
The following describes the behavior of the L2RAMW Module when in debug mode:
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No single-bit error interrupt is generated nor is any single-bit error address captured even when the
RAMOCCUR counter reaches the programmed single-bit error correction threshold.
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No uncorrectable error interrupt is generated nor is any double-bit error address captured.
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No address parity error interrupt is generated nor is any parity error address captured.
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The RAMUERRADDR register is not cleared by a read in debug mode.
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That is, if a double-bit error address is captured and is not read by the CPU before entering debug
mode, then it remains frozen during debug mode even if it is read.
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The RAMPERRADDR register is not cleared by a read in debug mode.
8.2.6 Diagnostic Test Procedure
1. Write test vectors DIAG_DATA_VECTOR_H, DIAG_DATA_VECTOR_L, DIAG_ECC, and
RAMADDRDEC_VECT with desire test irritants.
2. In RAMTEST, write TEST_ENABLE field with Ah and TEST_MODE field with the choice of inequality
or equality testing for redundant address decoding and SECDED multifunction diagnostics. Set up
proper values in DIAG_ECC, DIAG_DATA_VECTOR_L and DIAG_DATA_VECTOR_H registers. ECC
single bit or double bit read and write diagnostic errors will be generated if the values do not match.
3. In RAMTEST, write TRIGGER bit. Remember the trigger can only be enabled when TEST_ENABLE is
equal to Ah and RAMERRSTATUS[22,21,20,19,12,11,10, 4] bits are zero. Triggering diagnostic test
while the memory banks are busy will force the test to wait until the banks are free. Note all diagnostic
testing for two SECDEDs and compare logics of redundant address decode, two SECDED
malfunctions, data merging block are completed in one HCLK cycle even though the TRIGGER bit can
last one VCLK cycle.
4. Read back register bits RAMERRSTATUS[22,21,20,19,12,11,10, 4] and observe pass/fail status. No
error bit will be set if no error is detected in the diagnostic test. The diagnostic errors will also be sent
to ESM group 2 as "uncorrectable error type B".
