SPICS
SPIENA
SPICLK
SPISOMI
t
C2EDELAY
Basic Operation
1517
SPNU563A – March 2018
Copyright © 2018, Texas Instruments Incorporated
Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin
Option (MibSPIP)
28.2.6.4.4 Chip-Select-Active-to-ENA-Signal-Active-Time-Out (C2EDELAY)
C2EDELAY is used in master mode only and it applies only if the addressed slave generates an ENAble
signal as a hardware handshake response. C2EDELAY defines the maximum time between the SPI /
MibSPI activating the chip select signal and the addressed slave responding by activating the ENA signal.
C2EDELAY defines a time-out value as a multiple of SPI clocks. The SPI clock depends on whether data
format 0 or data format 1 is selected.
The timeout value is calculated as:
t
C2EDELAY
= C2EDELAY/SPIclock
Figure 28-20. Chip-Select-Active-to-ENA-Signal-Active-Timeout
NOTE:
•
If the slave device is not responding with the ENA signal before the time-out
value is reached, the TIMEOUT flag in SPIFLG register is set and an interrupt is
asserted if enabled.
•
If a time-out occurs the MibSPI clears the transmit request of the timed-out
buffer, sets the TIMEOUT flag for the current buffer and continues with the
transfer of the next buffer in the sequence that is enabled.
•
If C2TDELAY is programmed a non-zero value, then C2EDELAY will start only
after the C2TDELAY completes. This should be taken into consideration to
determine an optimum value of C2EDELAY.
28.2.6.5 Multiple Transfers to Same Slave and Variable Chip Select Setup and Hold Timing
This section gives information on the variable chip select setup and it shows how the CSHOLD bit is used
and how the multiple transfers to same slave is enabled in the device.
28.2.6.5.1 Variable Chip Select Setup and Hold Timing (Master Only)
In order to support slow slave devices, a delay counter can be configured to delay data transmission after
the chip select is activated. A second delay counter can be configured to delay the chip select deactivation
after the last data bit is transferred. Both delay counters are clocked with the peripheral clock (VCLK).
If a particular data format specifically does not require these additional set-up or hold times for the chip
select pins, then they can be disabled in the corresponding SPIFMTx register.
28.2.6.5.2 Hold Chip-Select Active
Some slave devices require the chip select signal to be held continuously active during several
consecutive data word transfers. Other slave devices require the chip select signal to be deactivated
between consecutive data word transfers.
CSHOLD is programmable in both master and slave modes of the multi-buffer mode of SPI. However, the
meaning of CSHOLD in master mode and slave mode are different.
NOTE:
If the CSHOLD bit is set within the current data control field, the programmed hold time and
the following programmed set-up time will not be applied between transactions.
