CAN Message Transfer
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SPNU563A – March 2018
Copyright © 2018, Texas Instruments Incorporated
Controller Area Network (DCAN) Module
27.9.2 Auto-Bus-On
Per default, after the DCAN has entered Bus-Off state, the CPU can start a Bus-Off-Recovery sequence
by resetting Init bit. If this is not done, the module will stay in Bus-Off state.
The DCAN provides an automatic Auto-Bus-On feature that is enabled by bit ABO in CAN Control
Register. If set, the DCAN will automatically start the Bus-Off-Recovery sequence. The sequence can be
delayed by a user-defined number of VCLK cycles that can be defined in Auto-Bus-On Time Register.
NOTE:
If the DCAN goes Bus-Off due to massive occurrence of CAN bus errors, it stops all bus
activities and automatically sets the Init bit. Once the Init bit has been reset by the CPU or
due to the Auto-Bus-On feature, the device will wait for 129 occurrences of Bus Idle (equal to
129 × 11 consecutive recessive bits) before resuming normal operation. At the end of the
Bus-Off recovery sequence, the error counters will be reset.
27.10 Interrupt Functionality
Interrupts can be generated on two interrupt lines:
1. DCAN0INT line
2. DCAN1INT line
These lines can be enabled by setting the IE0 and IE1 bits, respectively, in the CAN Control Register.
The DCAN provides three groups of interrupt sources: Message Object Interrupts, Status Change
Interrupts and Error Interrupts (see
and
).
The source of an interrupt can be determined by the interrupt identifiers Int0ID / Int1ID in the Interrupt
Register (see
). When no interrupt is pending, the register will hold the value zero.
Each interrupt line remains active until the dedicated field in the Interrupt Register DCAN INT (Int0ID /
Int1ID) again reach zero (this means the cause of the interrupt is reset), or until IE0 / IE1 are reset.
The value 0x8000 in the Int0ID field indicates that an interrupt is pending because the CAN Core has
updated (not necessarily changed) the Error and Status Register (Error Interrupt or Status Interrupt). This
interrupt has the highest priority. The CPU can update (reset) the status bits WakeUpPnd, RxOk, TxOk
and LEC by reading the Error and Status Register DCAN ES, but a write access of the CPU will never
generate or reset an interrupt.
Values between 1 and the number of the last message object indicates that the source of the interrupt is
one of the message objects, Int0ID resp. Int1ID will point to the pending message interrupt with the
highest priority. The Message Object 1 has the highest priority, the last message object has the lowest
priority.
An interrupt service routine that reads the message that is the source of the interrupt, may read the
message and reset the message object’s IntPnd at the same time (ClrIntPnd bit in the IF1/IF2 Command
Register). When IntPnd is cleared, the Interrupt Register will point to the next message object with a
pending interrupt.
27.10.1 Message Object Interrupts
Message Object interrupts are generated by events from the message objects. They are controlled by the
flags IntPND, TxIE and RxIE, that are described in
Message Object interrupts can be routed to either DCAN0INT or DCAN1INT line, controlled by the
Interrupt Multiplexer Register (see
).
