Designed for Safety Applications
107
SPNU563A – March 2018
Copyright © 2018, Texas Instruments Incorporated
Introduction
1.1
Designed for Safety Applications
The TMS570LC43x device architecture has been designed from the ground up to simplify development of
functionally safe systems. The basic architectural concept is known as a safe island approach. Power,
clock, reset, and basic processing function are protected to a high level of diagnostic coverage in
hardware. Some of the key features of the safe island region are:
•
Lockstep safety concept is also extended to the Vector Interrupt Module (VIM). Dual VIMs in lockstep
that detect failures at the controller's boundary on a cycle by cycle basis. VIMs internal RAM that
stores the vector addresses is also ECC protected.
•
ECC diagnostic for the datapath on the Level 1 cache memories as well as ECC on the Level 2 SRAM
and flash memories of the R5F core. The ECC controllers are located inside the CPU for each
respective memory interface. This approach has two key advantages:
–
The interconnect between CPU and the memory is also covered by the diagnostic.
–
The ECC logic itself is checked on a cycle by cycle basis.
•
Hardware BIST controllers that provide an extremely high level of diagnostic coverage for the lockstep
CPUs and SRAMs in the system, while executing faster and consuming less memory than equivalent
software-based self-test solutions.
•
Hardware BIST diagnostic also for both the N2HET timer coprocessors.
•
Interconnect between the masters and the level 2 memories contain built-in hardware safety diagnostic
logic that monitors the integrity of traffics in each cycle
–
Continuous monitoring of transactions going in and out of the interconnect.
–
Parity diagnostic on the address and control paths between all masters and slaves
–
BIST mode for diagnostic coverage of the interconnect.
–
ECC generation and evaluation for transactions on the datapath generated for some of the bus
masters.
•
Onboard voltage and reset monitoring logic
•
Onboard oscillator and PLL failure detection logic including a backup RC oscillator that can be utilized
upon failure
The TMS570LC43x device architecture also includes many features to simplify diagnostics of remaining
logic such as:
•
Continuous parity or ECC diagnostics on all peripheral memories.
•
Analog and digital loopback to test for shorts on I/O.
•
HW self-test and diagnostics on the ADC module to check integrity of both analog inputs and the ADC
core conversion function.
•
A DMA driven hardware engine for the background calculation of CRC signatures during data
transfers.
•
A centralized error reporting function including a status output pin to enable external monitoring of the
device status.
