2.19.2 CPU Mailbox Access
Mailbox Layout
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Table 2-26. Message Identifier Register (MSGID) Field Descriptions (continued)
Bit
Field
Value
Description
28:0
ID[28:0]
Message identifier
1
In standard identifier mode, if the IDE bit (MSGID.31) = 0, the message identifier is stored in bits
ID.28:18. In this case, bits ID.17:0 have no meaning.
0
In extended identifier mode, if the IDE bit (MSGID.31) = 1, the message identifier is stored in bits
ID.28:0.
Write accesses to the identifier can only be accomplished when the mailbox is disabled (CANME[
n
]
(CANME.31-0) = 0). During access to the data field, it is critical that the data does not change while the
CAN module is reading it. Hence, a write access to the data field is disabled for a receive mailbox.
For send mailboxes, an access is usually denied if the TRS (TRS.31-0) or the TRR (TRR.31-0) flag is set.
In these cases, an interrupt can be asserted. A way to access those mailboxes is to set CDR (MC.8)
before accessing the mailbox data.
After the CPU access is finished, the CPU must clear the CDR flag by writing a 0 to it. The CAN module
checks for that flag before and after reading the mailbox. If the CDR flag is set during those checks, the
CAN module does not transmit the message but continues to look for other transmit requests. The setting
of the CDR flag also stops the write-denied interrupt (WDI) from being asserted.
62
eCAN Registers
SPRU074F – May 2002 – Revised January 2009