Texas Instruments TMS320VC5509, Reference Manual

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Clock Generation in the Sample Rate Generator
3-7 Sample Rate Generator of the McBSP SPRU592E
Table 3 − 3. Polarity Options for the Input to the Sample Rate Generator
Input Clock Polarity Option Effect
on CLKS pin
†
CLKSP = 0 in SRGR2 Rising edge on CLKS pin generates rising edge on CLKG.
Rising edge on CLKS pin generates transitions on FSG.
CLKSP = 1 in SRGR2 Falling edge on CLKS pin generates rising edge on CLKG.
Falling edge on CLKS pin generates transitions on FSG.
McBSP internal
input clock Always positive polarity Rising edge of McBSP internal input clock generates rising
edge on CLKG.
on CLKR pin CLKRP
‡
= 0 in PCR Rising edge on CLKR pin generates rising edge on CLKG.
Rising edge on CLKR pin generates transitions on FSG.
CLKRP
‡
= 1 in PCR Falling edge on CLKR pin generates rising edge on CLKG.
Falling edge on CLKR pin generates transitions on FSG.
on CLKX pin CLKXP
‡
= 0 in PCR Rising edge on CLKX pin generates rising edge on CLKG.
Rising edge on CLKX pin generates transitions on FSG.
CLKXP
‡
= 1 in PCR Falling edge on CLKX pin generates rising edge on CLKG.
Falling edge on CLKX pin generates transitions on FSG.
†
Not all C55x devices have a CLKS pin; check the device-specific data manual.
‡
On TMS320VC5501 and TMS320VC5502 devices, the polarity of the sample rate generator input clock is always positive (rising
edge), regardless of CLKRP or CLKXP.
3.2.3 Choosing a Frequency for the Output Clock (CLKG)
The input clock (McBSP internal input clock or external clock) can be divided
down by a programmable value to drive CLKG. Regardless of the source to
the sample rate generator, the rising edge of CLKSRG generates CLKG and
FSG.
The first divider stage of the sample rate generator creates the output clock
from the input clock. This divider stage uses a counter that is preloaded with
the divide down value in the CLKGDV bits of SRGR1. The output of this stage
is the data clock (CLKG). CLKG has the frequency represented by the
following equation.
CLKG frequency +
Input clock frequency
( CLKGDV ) 1)
Thus, the input clock frequency is divided by a value between 1 and 256. When
CLKGDV is odd or equal to 0, the CLKG duty cycle is 50%. When CLKGDV
is an even value, 2p, representing an odd divide down, the high-state duration
is p+1 cycles and the low-state duration is p cycles.