Texas Instruments TMS320VC5509, Reference Manual

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Sample Rate Generator Registers (SRGR1 and SRGR2)
12-25 McBSP Registers SPRU592E
12.6 Sample Rate Generator Registers (SRGR1 and SRGR2)
Each McBSP has two sample rate generator registers of the form shown in
Figure 12
− 6. Table 12 − 7 and Table 12 − 8 describe the bits of SRGR1 and
SRGR2, respectively. The sample rate generator can generate a clock signal
(CLKG) and a frame-sync signal (FSG). The I/O-mapped registers SRGR1
and SRGR2 enable you to:
-
Select the input clock source for the sample rate generator (CLKSM, in
conjunction with the SCLKME bit of PCR)
-
Divide down the frequency of CLKG (CLKGDV)
-
Select whether internally-generated transmit frame-sync pulse are driven
by FSG or by activity in the transmitter (FSGM).
-
Specify the width of frame-sync pulses on FSG (FWID) and specify the
period between those pulses (FPER)
When an external source (via the CLKS, CLKR, or CLKX pin) provides the
input clock source for the sample rate generator:
-
If the CLKS pin provides the input clock, the CLKSP bit in SRGR2 allows
you to select whether the rising edge or the falling edge of CLKS triggers
CLKG and FSG. If the CLKX/CLKR pin is used instead of the CLKS pin,
the polarity of the input clock is selected with CLKXP/CLKRP of PCR.
-
The GSYNC bit of SRGR2 allows you to make CLKG synchronized to an
external frame-sync signal on the FSR pin, so that CLKG is kept in phase
with the input clock.
Notes:
1) Not all C55x devices have a CLKS pin; check the device-specific data
manual.
2) On TMS320VC5501 and TMS320VC5502 devices, the polarity of the
SRG input clock is always positive (rising edge), regardless of CLKRP
or CLKXP.
3) The clock synchronization provided through the GSYNC bit is not
supported on TMS320VC5501 and TMS320VC5502 devices.