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Texas Instruments TMS320VC5501 Instruction Cache Download Page 16

CPU Bits for Controlling the I-Cache

Instruction Cache

16

SPRU630C

2

CPU Bits for Controlling the I-Cache

Control of the I-Cache is maintained not only through the I-Cache registers but
also through three bits located in status register ST3_55 of the CPU. These
bits are highlighted in Figure 5. For more details about ST3_55, see the

TMS320C55x DSP CPU Reference Guide

(SPRU371).

Figure 5.

CAFRZ, CAEN, and CACLR Bits in ST3_55

15

14

13

12

11

8

CAFRZ

CAEN

CACLR

HINT

Reserved

R/W-0

R/W-0

R/W-0

7

6

5

4

3

2

1

0

CBERR

MPNMC

SATA

Reserved

CLKOFF

SMUL

SST

2.1

CAEN Bit to Enable or Disable the I-Cache

To enable the I-Cache, set the cache enable (CAEN) bit of ST3_55. To disable
the I-Cache, clear the CAEN bit. When disabled, the lines of the I-Cache data
arrays are not checked; instead, the I-Cache forwards instruction-fetch
requests directly to the external memory interface (EMIF).

For proper operation of the I-Cache, configure the I-Cache before enabling it
and disable the I-Cache before making any changes to its configuration.

A DSP reset forces CAEN = 0 (I-Cache disabled).

2.2

CACLR Bit to Flush the I-Cache

The flush operation is defined as the invalidation of all of the lines in the
I-Cache.

To flush the I-Cache, write 1 to the cache clear (CACLR) bit of ST3_55. In
response, all the line valid bits of the 2-way cache are cleared. The CACLR
bit remains 1 until the flush process is complete, at which time CACLR is
automatically reset to 0.

A DSP reset forces CACLR = 0 (no flush in process).

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Summary of Contents for TMS320VC5501

Page 1: ...TMS320VC5501 5502 DSP Instruction Cache Reference Guide SPRU630C June 2004 ...

Page 2: ...tute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction is...

Page 3: ...le the following number is the decimal number 4 shown in binary form 0100b Related Documentation From Texas Instruments The following documents describe the C55x devices and related support tools Copies of these documents are available on the Internet at www ti com Tip Enter the literature number in the search box provided at www ti com TMS320VC5501 Fixed Point Digital Signal Processor Data Manual...

Page 4: ...mmary of the instruction set a list of the instruction opcodes and a cross reference to the mnemonic instruction set TMS320C55x DSP Mnemonic Instruction Set Reference Guide literature number SPRU374 describes the TMS320C55x DSP mnemonic instructions individually Also includes a summary of the instruction set a list of the instruction opcodes and a cross reference to the algebraic instruction set T...

Page 5: ...Trademarks 5 Instruction Cache SPRU630C Trademarks TMS320C5000 TMS320C55x and C55x are trademarks of Texas Instruments Other trademarks are the property of their respective owners ...

Page 6: ...6 Instruction Cache SPRU630C This page is intentionally left blank ...

Page 7: ...16 2 2 CACLR Bit to Flush the I Cache 16 2 3 CAFRZ Bit to Freeze the Contents of the I Cache 17 3 Configuring and Enabling the I Cache 18 4 Timing Considerations 19 4 1 Hit Time 19 4 2 Miss Penalty 20 5 Power Emulation and Reset Considerations 21 5 1 Emulator Access 21 5 2 Effect of Setting a Software Breakpoint 21 5 3 Reconfiguration Required After a DSP Reset 21 6 I Cache Registers 22 6 1 Global...

Page 8: ...Flush Line Low Address Register ICFARL 24 8 I Cache Flush Line High Address Register ICFARH 24 9 I Cache Way Miss Counter Register ICWMC 25 Tables 1 Fetch Address Field Descriptions for the 2 Way Cache 13 2 Instruction Presence Check and I Cache Response 14 3 Summary of the I Cache Registers 22 4 I Cache Global Control Register ICGC Bits 23 5 I Cache Flush Line Low Address Register ICFARL Bits 24 ...

Page 9: ...unit CPU 1 Introduction Figure 1 shows how the I Cache fits into the DSP system CPU status register ST3_55 contains three cache control bits for enabling freezing and flushing the I Cache see section 2 on page 16 To configure the I Cache and check its status the CPU accesses a set of registers in the I Cache For storing instructions the I Cache contains one 2 way cache The 2 way cache uses 2 way s...

Page 10: ...st goes directly to the IPORT and then to the external memory interface EMIF The EMIF must read 32 bits from the external memory and then pass all 32 bits to the IPORT which in turn sends the data to the CPU Two things could happen if the instruction cache is enabled In the case of a cache hit the CPU request will be immediately serviced by the instruction cache and no data will be read from exter...

Page 11: ...ta array Each data array contains 512 lines 0 through 511 that the I Cache can fill one by one in response to misses in the 2 way cache Line valid LV bit array Each line has a line valid bit Once a line has been loaded its line valid bit is set Whenever the I Cache is flushed all 512 line valid bits are cleared invalidating all the lines For more information on flushing the I Cache see section 2 2...

Page 12: ...quests instructions it requests 32 bits at a time With each request the CPU sends a fetch address that indicates where to read the 32 bit requested word When a fetch request arrives the I Cache performs an instruction presence check that is it determines whether the requested word is available in the 2 way cache Section 1 2 2 describes the steps of the instruction presence check and explains the f...

Page 13: ...it words in the line should be read 1 0 Byte This field is not used by the I Cache but is the part of the fetch address that indicates the specific byte being addressed 1 2 2 Instruction Presence Check and the Corresponding I Cache Response As mentioned earlier when a fetch request arrives the I Cache performs an instruction presence check to determine whether the 32 bit requested word is availabl...

Page 14: ...ory block that contains the requested word is fetched and loaded into a line in the I Cache This line load process is illustrated in Figure 4 The I Cache uses the external memory interface EMIF to fetch the 4 word block that contains the requested word These four 32 bit words are written to the line in the I Cache one word at a time The I Cache delivers the requested word to the CPU as soon as the...

Page 15: ... the Line Load Process I Cache must load 2 way cache line Command EMIF to read four 32 bit words from external memory Is word received No Write word to line Yes it the requested word Is Yes Deliver word to I unit of CPU load done Line No Wait for next word No End Yes ...

Page 16: ... CAEN bit of ST3_55 To disable the I Cache clear the CAEN bit When disabled the lines of the I Cache data arrays are not checked instead the I Cache forwards instruction fetch requests directly to the external memory interface EMIF For proper operation of the I Cache configure the I Cache before enabling it and disable the I Cache before making any changes to its configuration A DSP reset forces C...

Page 17: ... cached prior to the freeze are still accessible in the case of an I Cache hit but the data arrays are not updated in response to an I Cache miss To re enable updates write 0 to CAFRZ A DSP reset forces CAFRZ 0 I Cache not frozen Note When the I Cache is frozen CAFRZ 1 each I Cache miss still causes a 4 word 16 byte fetch cycle in the EMIF It is recommended that you profile your code to minimize t...

Page 18: ... this section are described in section 6 page 22 The cache enable CAEN bit that is used to enable and disable the I Cache is described in section 2 1 page 16 Note Write to the control registers ICGC and ICWC only when the I Cache is disabled CAEN 0 in ST3_55 To initialize the I Cache write CE3Ch to ICGC Then set the cache enable bit CAEN of the CPU status register ST3_55 to send an enable request ...

Page 19: ...uested word to the CPU in the case of a hit when the word is present in the I Cache The hit time is either 1 or 2 CPU clock cycles An initial request a request that follows a period of inactivity has a hit time of 2 cycles Subsequent requests have a hit time of 1 cycle if J The requests are consecutive no inactivity in between and J The requests are to sequential addresses Subsequent requests have...

Page 20: ...tial access latency of the type of external memory that is used The position of the requested word in the I Cache line For example if the requested word is the third word of the line two words are fetched before the requested word Whether the four words are fetched in a burst access if synchronous memory is used 3 Three cycles for the I Cache to get the requested 32 bit word to the instruction fet...

Page 21: ...read the contents of the I Cache during the debug mode The contents of the I Cache are not modified by emulator read operations 5 2 Effect of Setting a Software Breakpoint During emulation If you set or remove a software breakpoint at an instruction the corresponding line in the I Cache is automatically invalidated 5 3 Reconfiguration Required After a DSP Reset After a DSP reset the I Cache is not...

Page 22: ...ine low address register Page 24 ICFARH Flush line high address register Page 24 ICWMC Way miss counter register Page 25 6 1 Global Control Register ICGC The TMS320C5501 5502 I Cache supports one 2 way cache Before enabling the I Cache use the global control register ICGC to initialize it You can write two legal values to ICGC CE3Ch to initialize the I Cache DE3Ch to force a line flush Do not writ...

Page 23: ...e to be flushed is contained in the flush line address registers ICFARL and ICFARH ICFARL contains the least significant 16 bits of the address associated with the line to be flushed ICFARH contains the most significant 8 bits of the address associated with the line to be flushed The address specified in these registers is a byte address See section 6 2 on page 24 for information about ICFARH and ...

Page 24: ...ers Figure 7 I Cache Flush Line Low Address Register ICFARL 15 0 LAL 15 0 R W 0 Table 5 I Cache Flush Line Low Address Register ICFARL Bits Bit Field Description 15 0 LAL Least significant 16 bits of the program address associated with the line to be flushed Figure 8 I Cache Flush Line High Address Register ICFARH 15 8 7 0 Reserved LAH 7 0 R 0 R W 0 Table 6 I Cache Flush Line High Address Register...

Page 25: ...the register is read or loaded with a different value Your program can read the value and write that value Figure 9 I Cache Way Miss Counter Register ICWMC 15 0 MISSCNT R W 0 Legend R Read W Write n Value after reset x Value after reset is not defined Table 7 I Cache Way Miss Counter Register ICWMC Bits Bit Field Description 15 0 MISSCNT A counter to count the number of mis compares for the 2 way ...

Page 26: ...Instruction Cache 26 SPRU630C This page is intentionally left blank ...

Page 27: ...0C from SPRU630B which was released in August 2003 Changes that were made since the last revision are listed in the following table Page Additions Modifications Deletions 10 Added IPORT block to Figure 1 10 and 11 Revised paragraphs 2 4 in Section 1 13 Added bit number 12 in Figure 3 ...

Page 28: ...Instruction Cache 28 SPRU630C This page is intentionally left blank ...

Page 29: ...or controlling I Cache 16 D data array 11 diagram of I Cache 10 disable I Cache 16 DSP reset reconfiguring I Cache after 21 E emulator access 21 enable I Cache as part of initialization procedure 18 CAEN bit description 16 external memory interface EMIF 10 F fetch address how I Cache uses 13 flush I Cache 16 flush line address registers ICFARL and ICFARH 24 FLUSHLINE bit of ICGC described in table...

Page 30: ... line load process 14 line valid LV bit array 11 LRU algorithm 11 M memory banks 11 miss 13 miss penalty 20 MISSCNT bits of ICWMC described in table 25 shown in figure 25 O operation of I Cache 12 P presence check 13 R reconfiguration of I Cache after DSP reset 21 registers of I Cache 22 S software breakpoint effect on I Cache 21 status register ST3_55 of CPU 16 synchronous memory miss penalty 20 ...

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