Advisory
SDFM: Dynamically Changing Threshold Settings (LLT, HLT), Filter Type, or COSR
Settings Will Trigger Spurious Comparator Events
Revisions Affected
0, A, B
Details
When SDFM comparator settings—such as filter type, lower/upper threshold, or
comparator OSR (COSR) settings—are dynamically changed during run time, spurious
comparator events will be triggered. The spurious comparator event will trigger a
corresponding CPU interrupt, CLA task, ePWM X-BAR events, and GPIO output X-BAR
events if configured appropriately.
Workaround
When comparator settings need to be changed dynamically, follow the procedure below to
ensure spurious comparator events do not generate a CPU interrupt, CLA task, or
X-BAR events (ePWM X-BAR/GPIO output X-BAR events):
1. Disable the comparator filter.
2. Delay for at least a latency of the comparator 3 SD-Cx clock cycles.
3. Change comparator filter settings such as filter type, COSR, or lower/upper threshold.
4. Delay for at least a latency of the comparator 5 SD-Cx clock cycles.
5. Enable the comparator filter.
Advisory
SDFM: Dynamically Changing Data Filter Settings (Such as Filter Type or DOSR)
Will Trigger Spurious Data Acknowledge Events
Revisions Affected
0, A, B
Details
When SDFM data settings—such as filter type or DOSR settings—are dynamically
changed during run time, spurious data-filter-ready events will be triggered. The spurious
data-ready event will trigger a corresponding CPU interrupt, CLA task, and DMA trigger if
configured appropriately.
Workaround
When SDFM data filter settings need to be changed dynamically, follow the procedure
below to ensure spurious data-filter-ready events are not generated:
1. Disable the data filter.
2. Delay for at least a latency of the data 3 SD-Cx clock cycles.
3. Change data filter settings such as filter type and DOSR.
4. Delay for at least a latency of the data 5 SD-Cx clock cycles.
5. Enable the data filter.
Advisory
SDFM: Two Back-to-Back Writes to SDCPARMx Register Bit Fields CEVT1SEL,
CEVT2SEL, and HZEN Within Three SD-Modulator Clock Cycles can Corrupt SDFM
State Machine, Resulting in Spurious Comparator Events
Revisions Affected
0, A, B
Details
Back-to-back writes to SDCPARMx register bit fields CEVT1SEL, CEVT2SEL, and HZEN
within three SD-modulator clock cycles can potentially corrupt the SDFM state machine,
resulting in spurious comparator events, which can potentially trigger CPU interrupts, CLA
tasks, ePWM XBAR events, and GPIO output X-BAR events if configured appropriately.
Workaround
Avoid back-to-back writes within three SD-modulator clock cycles or have the SDCPARMx
register bit fields configured in one register write.
Silicon Revision B Usage Notes and Advisories
SPRZ439G – JANUARY 2017 – REVISED AUGUST 2022
TMS320F28004x Real-Time MCUs Silicon Errata
Silicon Revisions B, A, 0
13
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