2.13.2 Trigger Source Priority
2.13.3 Dequeue Priority
2.13.4
System (Transfer Controller) Priority
2.14 EDMA3 Operating Frequency (Clock Control)
2.15 Reset Considerations
EDMA3 Operating Frequency (Clock Control)
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If a DMA channel is associated with more than one trigger source (event trigger, manual trigger, and chain
trigger), and if multiple events are set simultaneously for the same channel (ER.E
n
= 1, ESR.E
n
= 1,
CER.E
n
= 1), then the EDMA3CC always services these events in the following priority order: event
trigger (via ER) is higher priority than chain trigger (via CER) and chain trigger is higher priority than
manual trigger (via ESR).
This implies that if for channel 0, both ER.E0 = 1 and CER.E0 = 1 at the same time, then the ER.E0 event
is always queued before the CER.E0 event.
The priority of the associated transfer request (TR) is further mitigated by which event queue is being used
for event submission (dictated by DMAQNUM and QDMAQNUM). For submission of a TR to the transfer
controller, events need to be dequeued from the event queues. Q0 has higher dequeue priority then Q1.
In other words, if there are multiple events in both Q0 and Q1, then the transfer requests associated with
events in Q0 will get submitted to TC0 prior to any transfer requests associated with events in Q1 getting
submitted to TC1.
Note:
If there are outstanding events in both queues, then the channel controller will always submit
requests to TC0, before submitting requests to TC1, even if TC0 is busy processing earlier
transfer requests and TC1 is available. This can cause delays in submission of requests on
Q1. Therefore, it is recommended to reserve the higher priority Q0/TC0 for submission of
urgent, small, real-time sensitive transfers and allocate Q1/TC1 for longer, nonreal-time
sensitive transfers.
Each transfer controller has a programmed system priority (programmed via the QUEPRI) that is
implemented when multiple masters in the system are vying for the same endpoint. The priority of the
associated transfer request (TR) is further mitigated by system priority setting of the transfer controller.
This priority is necessary when several masters are submitting requests to the main switched central
resource (SCR), which in turn has to arbitrate the requests from these masters.
Note:
The default priority for both TC0 and TC1 is the same, 0 or highest priority relative to other
masters (like EMAC, VPSS, etc.). It is recommended that this priority be changed based on
system level considerations, such as real-time deadlines for all masters including the priority
of the transfer controllers with respect to each other. (The priority configuration registers for
other masters are either present within the memory-map of the master or implemented as a
chip level register, see the device-specific data manual).
The EDMA3 channel controller and transfer controller are clocked from PLL1. The EDMA3 system runs at
SYSCLK3.
A hardware reset resets the EDMA3 (EDMA3CC and EDMA3TC) and the EDMA3 configuration registers.
The PaRAM memory contents are undefined after device reset and you should not rely on parameters to
be reset to a known state. The PaRAM set must be initialized to a desired value before it is used.
EDMA3 Architecture
62
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Summary of Contents for TMS320DM357
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