General-Purpose Register Files
2-5
CPU Data Paths and Control
Figure 2–3 illustrates the register storage scheme for 40-bit long data. Opera-
tions requiring a long input ignore the 24 MSBs of the odd register. Operations
producing a long result zero-fill the 24 MSBs of the odd register. The even
register is encoded in the opcode.
Figure 2–3. Storage Scheme for 40-Bit Data in a Register Pair
ÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍ
31
0
31
0
Odd register
Even register
39
32
31
0
Zero-filled
40-bit data
39
32
31
0
40-bit data
Á
Á
ÁÁ
ÁÁ
Á
ÁÁ
Odd register
Even register
Read from registers
Write to registers
Ignored
7
8
