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TMS320C6670 Peripheral Information and Electrical Specifications
Copyright 2012 Texas Instruments Incorporated
SPRS689D—March 2012
Multicore Fixed and Floating-Point System-on-Chip
TMS320C6670
7.13 SPI Peripheral
The Serial Peripheral Interconnect (SPI) module provides an interface between the DSP and other SPI-compliant
devices. The primary intent of this interface is to allow for connection to a SPI ROM for boot. The SPI module on
C6670 is supported only in Master mode. Additional chip-level components can also be included, such as
temperature sensors or an I/O expander.
7.13.1 SPI Electrical Data/Timing
Table 7-68
SPI Timing Requirements
See
)
No.
Min
Max
Unit
Master Mode Timing Diagrams — Base Timings for 3 Pin Mode
7
tsu(SOMI-SPC)
Input setup time, SPIx_SOMI valid before receive edge of SPIx_CLk. Polarity = 0 Phase = 0
2
ns
7
tsu(SOMI-SPC)
Input setup time, SPIx_SOMI valid before receive edge of SPIx_CLk. Polarity = 0 Phase = 1
2
ns
7
tsu(SOMI-SPC)
Input setup time, SPIx_SOMI valid before receive edge of SPIx_CLk. Polarity = 1 Phase = 0
2
ns
7
tsu(SOMI-SPC)
Input setup time, SPIx_SOMI valid before receive edge of SPIx_CLk. Polarity = 1 Phase = 1
2
ns
8
th(SPC-SOMI)
Input hold time, SPIx_SOMI valid after receive edge of SPIx_CLK. Polarity = 0 Phase = 0
5
ns
8
th(SPC-SOMI)
Input hold time, SPIx_SOMI valid after receive edge of SPIx_CLK. Polarity = 0 Phase = 1
5
ns
8
th(SPC-SOMI)
Input hold time, SPIx_SOMI valid after receive edge of SPIx_CLK. Polarity = 1 Phase = 0
5
ns
8
th(SPC-SOMI)
Input hold time, SPIx_SOMI valid after receive edge of SPIx_CLK. Polarity = 1 Phase = 1
5
ns
End of Table 7-68
Table 7-69
SPI Switching Characteristics (Part 1 of 2)
)
No.
Parameter
Min
Max
Unit
Master Mode Timing Diagrams — Base Timings for 3 Pin Mode
1
tc(SPC)
Cycle time, SPIx_CLK, all master modes
3*P2
(1)
ns
2
tw(SPCH)
Pulse width high, SPIx_CLK, all master modes
0.5*(3*P2) - 1
ns
3
tw(SPCL)
Pulse width low, SPIx_CLK, all master modes
0.5*(3*P2) - 1
ns
4
td(SIMO-SPC)
Setup (Delay), initial data bit valid on SPIx_SIMO to initial edge on SPIx_CLK.
Polarity = 0, Phase = 0.
5
ns
4
td(SIMO-SPC)
Setup (Delay), initial data bit valid on SPIx_SIMO to initial edge on SPIx_CLK.
Polarity = 0, Phase = 1.
5
ns
4
td(SIMO-SPC)
Setup (Delay), initial data bit valid on SPIx_SIMO to initial edge on SPIx_CLK
Polarity = 1, Phase = 0
5
ns
4
td(SIMO-SPC)
Setup (Delay), initial data bit valid on SPIx_SIMO to initial edge on SPIx_CLK
Polarity = 1, Phase = 1
5
ns
5
td(SPC-SIMO)
Setup (Delay), subsequent data bits valid on SPIx_SIMO to initial edge on
SPIx_CLK. Polarity = 0 Phase = 0
2
ns
5
td(SPC-SIMO)
Setup (Delay), subsequent data bits valid on SPIx_SIMO to initial edge on
SPIx_CLK Polarity = 0 Phase = 1
2
ns
5
td(SPC-SIMO)
Setup (Delay), subsequent data bits valid on SPIx_SIMO to initial edge on
SPIx_CLK Polarity = 1 Phase = 0
2
ns
5
td(SPC-SIMO)
Setup (Delay), subsequent data bits valid on SPIx_SIMO to initial edge on
SPIx_CLK Polarity = 1 Phase = 1
2
ns
6
toh(SPC-SIMO)
Output hold time, SPIx_SIMO valid after receive edge of SPIx_CLK except for
final bit. Polarity = 0 Phase = 0
0.5*tc - 2
ns
6
toh(SPC-SIMO)
Output hold time, SPIx_SIMO valid after receive edge of SPIx_CLK except for
final bit. Polarity = 0 Phase = 1
0.5*tc - 2
ns
6
toh(SPC-SIMO)
Output hold time, SPIx_SIMO valid after receive edge of SPIx_CLK except for
final bit. Polarity = 1 Phase = 0
0.5*tc - 2
ns
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