Asynchronous Interface
9-52
9.6.1
TMS320C6201/C6202/C6701 ROM Modes
The EMIF supports 8- and 16-bit-wide ROM access modes which are selected
by the MTYPE field in the EMIF CE space control registers. In reading data
from these narrow memory spaces, the EMIF packs multiple reads into one
32-bit-wide value. This mode is primarily intended for word accesses to 8-bit
and 16-bit ROM devices. The following restrictions apply:
-
Read operations always read 32 bits, regardless of the access size or the
memory width.
-
The address is shifted up appropriately to provide the correct address to
the narrow memory. The shift amount is 1 for 16-bit ROM and 2 for 8-bit
ROM. Thus, the high address bits are shifted out, and accesses wrap
around if the CE space spans the entire EA bus. Table 9–19 shows the ad-
dress bits on the EA bus during an access to CE1 space for all possible
asynchronous memory widths.
-
The EMIF always reads the lower addresses first and packs these into the
LSbytes. It packs subsequent accesses into the higher order bytes. Thus,
the expected packing format in ROM is always little-endian, regardless of
the value of the LENDIAN bit.
Table 9–19. Byte Address to EA Mapping for Asynchronous Memory Widths
EA Line
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
Width
Logical Byte Address
32
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
16
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
8
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
9.6.1.1
8-Bit ROM Mode
In 8-bit ROM mode, the address is left-shifted by 2 to create a byte address
on EA to access byte-wide ROM. The EMIF always packs four consecutive
bytes aligned on a 4-byte boundary (byte address = 4N) into a word access.
The bytes are fetched in the following address order: 4N, 4N + 1, 4N + 2,
4N + 3. Bytes are packed into the 32-bit word from MSByte to LSByte in the
following little endian order: 4N + 3, 4N + 2, 4N + 1, 4N.
