Texas Instruments TMS320C28x, Reference Manual

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Status Register ST1
2-35 Central Processing Unit
Reserved
Bit 10
Reserved . This bit is reserved. Writes to this bit have no effect.
OBJMODE
Bit 9
Object compatibility mode bit . This mode is used to select between C27x object
mode (OBJMODE == 0) and C28x object mode (OBJMODE == 1) compatibility. This bit
is set by the ”C28OBJ” (or ”SETC OBJMODE”) instructions. This bit is cleared by the
”C27OBJ” (or ”CLRC OBJMODE”) instructions. The pipeline is flushed when setting or
clearing this bit using the given instructions. This bit is saved and restored by interrupts
and when restoring the ST1 register. This bit is set to 0 on reset.
AMODE
Bit 8
Address mode bit . This mode, in conjunction with the PAGE0 mode bit, is used to se-
lect the appropriate addressing mode decodes. This bit is set by the “LPADDR” (”SETC
AMODE”) instructions. This bit is cleared by the ”C28ADDR” (or ”CLRC AMODE”) in-
structions. The pipeline is not flushed when setting or clearing this bit using the given
instructions. This bit is saved and restored by interrupts and when restoring the ST1
register. This bit is set to 0 on reset.
Note: Setting PAGE0 = AMODE = 1 will generate an illegal instruction trap ONLY for
instructions that decode a memory or register addressing mode field (loc16 or loc32).
IDLESTAT
Bit 7
IDLE status bit. This ready-only bit is set when the IDLE instruction is executed. It is
cleared by any one of the following events:
- An interrupt is serviced.
- An interrupt is not serviced but takes the CPU out of the IDLE state.
- A valid instruction enters the instruction register (the register that holds the instruction
currently being decoded).
-
A device reset occurs.
When the CPU services an interrupt, the current value of IDLESTAT is saved on the
stack (when ST1 is saved on the stack), and then IDLESTAT is cleared. Upon return
from the interrupt, IDLESTAT is not restored from the stack.
EALLOW
Bit 6
Emulation access enable bit. This bit, when set, enables access to emulation and
other protected registers. Set this bit by using the EALLOW instruction and clear this bit
by using the EDIS instruction. See the data sheet for a particular device to determine
the registers that are protected.
When the CPU services an interrupt, the current value of EALLOW is saved on the
stack (when ST1 is saved on the stack), and then EALLOW is cleared. Therefore, at the
start of an interrupt service routine (ISR), access to protected registers is disabled. If the
ISR must access protected registers, it must include an EALLOW instruction. At the end
of the ISR, EALLOW can be restored by the IRET instruction.
LOOP
Bit 5
Loop instruction status bit. LOOP is set when a loop instruction (LOOPNZ or
LOOPZ) reaches the decode 2 phase of the pipeline. The loop instruction does not end
until a specified condition is met. When the condition is met, LOOP is cleared. LOOP is
a read-only bit; it is not affected by any instruction except a loop instruction.