Texas Instruments TMS320C28x, Reference Manual

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Architecture Changes
F-3 Migration From C27x to C28x
A brief description of the register modifications is given below:
XT(32), TL(16): The T register is increased to 32-bits and called the XT register. The existing C27x T register
portion represents the upper 16-bits of the new 32-bit register. The additional 16-bits, called
the TL portion, represents the lower 16-bits.
XAR0,..,XAR7(32): All of the AR registers are stretched to 32-bits. This enables a full 22-bit address. For
addressing operations, only the lower 22-bits of the registers are used, the upper 10-bits
are ignored. For operations between the ACC, all 32-bits are valid (register addressing
mode @XARx). For 16-bit operations to the low 16-bit of the registers (register addressing
mode @ARx), the upper 16-bits are ignored.
RPC(22): This is the return PC register. When a call operation is performed, the return address is
saved in the RPC register and the old value in the RPC is saved on the stack (in two 16-bit
operations). When a return operation is performed, the return address is read from the RPC
register and the value on the stack is written into the RPC register (in two 16-bit operations).
The net result is that return operations are faster (4 instead of 8 cycles)
SP(16): By default the C28x SP register is initialized to 0x400 after a reset.
ST0 (16): Shaded items indicate a change or addition from the C27x
Table F − 1. ST0 Register Bits
Bit(s) Mnemonic Description Reset Value R/W
0 SXM Sign Extension Mode Bit 0 R/W
1 OVM Overflow Mode Bit 0 R/W
2 TC Test Control Bit 0 R/W
3 C Carry Bit 0 R/W
4 Z Zero Condition Bit 0 R/W
5 N Negative Condition Bit 0 R/W
6 V Overflow Condition Bit 0 R/W
9:7 PM Product Shift Mode 0 (+1 shift) R/W
15:10 OVC/OVCU ACC Overflow Counter 0 R/W
PM: Functionality of the Product Shift Mode changes if the AMODE bit in ST1 is set to 1. C27x
users will not modify the AMODE bit and PM will function as they did on the C27x.
OVC/OVCU: The overflow counter is modified so that it behaves differently for signed or unsigned
operations. For signed operations (OVC), it behaves as it does on the C27x (increment
for positive overflow, decrement for negative underflow of a signed number). For
unsigned operations (OVCU), the overflow counter increments for an ADD operation
when there is a carry generated and decrements for a SUB operation when a borrow is
generated. Basically, in unsigned mode, the OVCU behaves like a carry (C) counter and
in signed mode the OVC behaves like an overflow (V) counter.