Texas Instruments TMS320C28x, Reference Manual

Page: 490 / 695

SUB ACC,loc16 << #0...16
6-333
SUB ACC,loc16 << #0...16 Subtract Shifted Value From Accumulator
SYNTAX OPTIONS OPCODE OBJMODE RPT CYC
SUB ACC,loc16 << #0
1010 1110 LLLL LLLL
1 Y N+1
1000 0000 LLLL LLLL
0 − 1
SUB ACC,loc16 << #1..15
0101 0110 0000 0000
0000 SHFT LLLL LLLL
1 Y N+1
1000 SHFT LLLL LLLL
0 − 1
SUB ACC,loc16 << #16
0000 0100 LLLL LLLL
X Y N+1
Operands ACC Accumulator register
loc16 Addressing mode (see Chapter 5)
#0..16 Shift value (default is ”<< #0” if no value specified)
Description Subtract the left-shifted 16-bit location pointed to by the ”loc16” addressing
mode from the ACC register. The shifted value is sign extended if sign
extension mode is turned on (SXM=1) else the shifted value is zero extended
(SXM= 0). The lower bits of the shifted value are zero filled:
if(SXM = 1) // sign extension mode enabled
ACC = ACC − S:[loc16] << shift value;
else
// sign extension mode disabled
ACC = ACC − 0:[loc16] << shift value;
Flags and
Modes
Z
After the subtraction, the Z flag is set if ACC is zero, else Z is cleared.
N After the subtraction, the N flag is set if bit 31 of the ACC is 1, else Z is
cleared.
C If the subtraction generates a borrow, C is cleared; otherwise C is set.
Exception: If a shift of 16 is used, the SUB instruction can clear C but not set
it.
V If an overflow occurs, V is set; otherwise V is not affected.
OVC If(OVM = 0, disabled) then if the operation generates a positive overflow,
then the counter is incremented and if the operation generates a negative
overflow, then the counter is decremented. If(OVM = 1, enabled) then the
counter is not affected by the operation.
SXM If sign extension mode bit is set; then the 16-bit operand, addressed by the
”loc16” field, will be sign extended before the addition. Else, the value will be
zero extended.
OVM If overflow mode bit is set; then the ACC value will saturate maximum
positive (0x7FFF FFFF) or maximum negative (0x8000 0000) if the
operation overflowed.