Texas Instruments TMS320C28x, Reference Manual

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CPU Registers
2-14
2.2.7 Program Counter (PC)
When the pipeline is full, the 22-bit program counter (PC) always points to the
instruction that is currently being processed — the instruction that has just
reached the decode 2 phase of the pipeline. Once an instruction reaches this
phase of the pipeline, it cannot be flushed from the pipeline by an interrupt. It
is executed before the interrupt is taken. The pipeline is discussed in
Chapter 4.
2.2.8 Return Program Counter (RPC)
When a call operation is performed using the LCR instruction, the return ad-
dress is saved in the RPC register and the old value in the RPC is saved on
the stack (in two 16-bit operations). When a return operation is performed us-
ing the LRETR instruction, the return address is read from the RPC register
and the value on the stack is written into the RPC register (in two 16-bit opera-
tions). Other call instructions do not use the RPC register. For more informa-
tion, see the instructions in Chapter 6.
2.2.9 Status Registers (ST0, ST1)
The C28x has two status registers, ST0 and ST1, which contain various flag
bits and control bits. These registers can be stored into and loaded from data
memory, enabling the status of the machine to be saved and restored for sub-
routines.
The status bits have been organized according to when the bit values are mo-
dified in the pipeline. Bits in ST0 are modified in the execute phase of the pipe-
line; bits in ST1 are modified in the decode 2 phase. (For details about the pipe-
line, see Chapter 4.) The status bits are described in detail in sections 2.3
(ST0) and 2.4 (ST1). Also, ST0 and ST1 are included in Appendix A,
Register
Quick Reference .
2.2.10 Interrupt-Control Registers (IFR, IER, DBGIER)
The C28x CPU has three registers dedicated to the control of interrupts:
-
Interrupt flag register (IFR)
-
Interrupt enable register (IER)
-
Debug interrupt enable register (DBGIER)
These registers handle interrupts at the CPU level. Devices with a peripheral
interrupt expansion (PIE) block will have additional interrupt control as part of
the PIE module.
The IFR contains flag bits for maskable interrupts (those that can be enabled
and disabled with software). When one of these flags is set, by hardware or