Texas Instruments TMS320C28x, Reference Manual

Page: 342 / 695

MOVAD T, loc16
6-185
MOVAD T, loc16 Load T Register
SYNTAX OPTIONS OPCODE OBJMODE RPT CYC
MOVAD T, loc16
1010 0111 LLLL LLLL
1 N 1
Operands T Upper 16 bits of the multiplicand register (XT)
loc16 Addressing mode (see Chapter 5)
Note: For this operation, register-addressing modes cannot be used. The modes are: @ARn,
@AH, @AL, @PH, @PL, @SP, @T. An illegal instruction trap will be generated.
Description Load the T register with the 16-bit content of the location pointed to by the
“loc16” addressing mode and then load the next highest 16-bit location
pointed to by “loc16” with the content of T. In addition, add the content of the P
register, shifted by the amount specified by the product shift mode (PM) bits,
to the content of the ACC register:
T = [loc16];
[loc16 + 1] = T;
ACC = ACC + P << PM;
Flags and
Modes
N
After the operation, if bit 31 of the ACC register is 1, then the N bit is set;
otherwise, N is cleared.
Z
After the operation, if the value of ACC is zero, then the Z bit is set; otherwise
Z is cleared.
C
If the addition generates a carry, the C bit is set; otherwise, C is cleared.
V If an overflow occurs, V is set; otherwise V is not affected
OVC If overflow mode is disabled; and if the operation generates a positive
overflow, then the counter is incremented. If overflow mode is disabled; and if
the operation generates a negative overflow, then the counter is
decremented.
OVM If overflow mode bit is set; then the ACC value will saturate maximum
positive (0x7FFFFFFF) or maximum negative (0x80000000) if the operation
overflows.
PM The value in the PM bits sets the shift mode for the output operation from the
product register. If the product shift value is positive (logical left shift
operation), then the low bits are zero filled. If the product shift value is
negative (arithmetic right shift operation), the upper bits are sign extended.