Texas Instruments TMS320C28x, Reference Manual

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LSLL ACC,T
6-139
LSLL ACC,T Logical Shift Left by T (4:0)
SYNTAX OPTIONS OPCODE OBJMODE RPT CYC
LSLL ACC,T
0101 0110 0011 1011
1 − 1
Operands ACC Accumulator register
T Upper 16 bits of the multiplicand (XT) register
T Upper 16 bits of the multiplicand register (XT)
Description Perform a logical shift left on the content of the ACC register by the amount
specified by the five least significant bits of the T register, T(4:0) = 0 … 31.
Higher order bits are ignored. During the shift, the low order bits of the ACC
register are zero filled. If T specifies a shift of 0, then C is cleared; otherwise,
C is filled with the last bit to be shifted out of the ACC register:
0
C
ACC
ACC
Last bit out or cleared
Discard
other bits
Left shift
(Contents of T (4:0)
Flags and
Modes
Z After the shift, the Z flag is set if the ACC value is zero, else Z is cleared. Even
if the T register specifies a shift of 0, the content of the ACC register is still
tested for the zero condition and Z is affected.
N After the shift, the N flag is set if bit 31 of the ACC is 1, else N is cleared. Even
if the T register specifies a shift of 0, the content of the ACC register is still
tested for the negative condition and N is affected.
Repeat This instruction is not repeatable. If this instruction follows the RPT
instruction, it resets the repeat counter (RPTC) and executes only once.
Example
; Logical shift left contents of VarA by VarB:
MOVL ACC,@VarA ; ACC = VarA
MOV T,@VarB ; T = VarB (shift value)
LSLL ACC,T ; Logical shift left ACC by T(4:0)
MOVL @VarA,ACC ; Store result into VarA