Texas Instruments TMS320C28x, Reference Manual

Page: 29 / 695

Memory Interface
1-11 Architectural Overview
Table 1 − 3. Special Bus Operations
Instruction
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Special Bus Operation
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
PREAD
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
This instruction reads a data value rather than an instruction from pro-
gram space. It then transfers that value to data space or a register.
For the read from program space, the CPU places the source address
on the program address bus (PAB), sets the appropriate program-
space select signals, and reads the data value from the program-read
data bus (PRDB).
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
PWRITE
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
This instruction writes a data value to program space. The value is
read from from data space or a register.
For the write to program space, the CPU places the destination ad-
dress on the program address bus (PAB), sets the appropriate pro-
gram-space select signals, and writes the data value to the data-/pro-
gram-write data bus (DWDB).
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
MAC
DMAC
QMACL
IMACL
XMAC
XMACD
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
As part of their operation, these instructions multiply two data values,
one of which is read from program space.
For the read from program space, the CPU places the program-space
source address on the program address bus (PAB), sets the appropri-
ate program-space select signals, and reads the program data value
from the program read data bus (PRDB).
1.4.3 Alignment of 32-Bit Accesses to Even Addresses
The C28x CPU expects memory wrappers or peripheral-interface logic to align
any 32-bit read or write to an even address. If the address-generation logic
generates an odd address, the CPU must begin reading or writing at the pre-
vious even address. This alignment does not affect the address values gener-
ated by the address-generation logic.
Most instruction fetches from program space are performed as 32-bit read op-
erations and are aligned accordingly. However, alignment of instruction
fetches are effectively invisible to a programmer. When instructions are stored
to program space, they do not have to be aligned to even addresses. Instruc-
tion boundaries are decoded within the CPU.
You need to be concerned with alignment when using instructions that perform
32-bit reads from or writes to data space.