11.5 CPU Arbitration
Typically, DMA activity is independent of the CPU activity. Under the circumstance where both the DMA and
the CPU are attempting to access memory or a peripheral register within the same interface concurrently, an
arbitration procedure will occur. The one exception is with the memory mapped (PF0) ADC registers, which do
not create a conflict when read by both the CPU and the DMA simultaneously, even if different addresses are
accessed. Any combined accesses between the different interfaces, or where the CPU access is outside of the
interface that the DMA is accessing do not create a conflict.
The interfaces which internally contain conflicts are:
• L5 RAM
• L6 RAM
• L7 RAM
• L8 RAM
• McBSP Peripheral Frame 3
• ePWM/HRPWM Peripheral Frame 3
• USB Peripheral Frame 3
If the CPU and the DMA make an access to the same interface in the same cycle, the DMA has priority and the
CPU is stalled.
If a CPU access to an interface is in progress and another CPU access to the same interface is pending,
for example, the CPU is performing a write operation and a read operation from the CPU is pending, then a
DMA access to that same interface has priority over the pending CPU access when the current CPU access
completes.
Note
If the CPU is performing a read-modify-write operation and the DMA performs a write to the same
location, the DMA write may be lost if the operation occurs in between the CPU read and the CPU
write. For this reason, it is advised not to mix such CPU accesses with DMA accesses to the same
locations.
In the case of RAM, a ping-pong scheme can be implemented to avoid the CPU and the DMA accessing the
same RAM block concurrently, thus avoiding any stalls or corruption issues.
11.6 Channel Priority
Two priority schemes exist when determining channel priority: Round-robin mode and Channel 1 high-priority
mode.
11.6.1 Round-Robin Mode
In this mode, all channels have
equal
priority and each enabled channel is serviced in round-robin fashion as
follows:
CH1 → CH2 → CH3 → CH4 → CH5 → CH6 → CH1 → CH2 → …
In the case above, after each channel has transferred a burst of words, the next channel is serviced. You can
specify the size of the burst for each channel. Once CH6 (or the last enabled channel) has been serviced, and
no other channels are pending, the round-robin state machine enters an idle state.
From the idle state, channel 1 (if enabled) is always serviced first. However, if the DMA is currently processing
another channel x, all other pending channels between x and the end of the round are serviced before CH1. It is
in this sense that all the channels are of
equal
priority. For instance, take an example where CH1, CH4, and CH5
are enabled in round-robin mode and CH4 is currently being processed. Then CH1 and CH5 both receive an
interrupt trigger from their respective peripherals before CH4 completes. CH1 and CH5 are now both pending.
When CH4 completes its burst, CH5 will be serviced next. Only after CH5 completes will CH1 be serviced. Upon
completion of CH1, if there are no more channels pending, the round-robin state machine will enter an idle state.
Direct Memory Access (DMA) Module
SPRUH18I – JANUARY 2011 – REVISED JUNE 2022
TMS320x2806x Microcontrollers
733
Copyright © 2022 Texas Instruments Incorporated
Summary of Contents for TMS320 2806 Series
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