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Figure 8-23. Interrupt Select 7 and 8 Register (INTSEL7N8)
15
14
13
12
8
Reserved
INT8CONT
INT8E
INT8SEL
R-0
R/W-0
R/W-0
R/W-0
7
6
5
4
0
Reserved
INT7CONT
INT7E
INT7SEL
R-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Figure 8-24. Interrupt Select 9 and 10 Register (INTSEL9N10)
15
8
Reserved
R-0
7
6
5
4
0
Reserved
INT9CONT
INT9E
INT9SEL
R-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 8-11. Interrupt Select Register (INTSELxNy) Field Descriptions
Bit
Field
Value
Description
15
Reserved
0
Reserved
14
INTyCONT
ADCINTy Continuous Mode Enable
0
No further ADCINTy pulses are generated until ADCINTy flag (in ADCINTFLG register) is
cleared by user.
1
ADCINTy pulses are generated whenever an EOC pulse is generated irrespective if the
flag bit is cleared or not.
13
INTyE
ADCINTy Interrupt Enable
0
ADCINTy is disabled.
1
ADCINTy is enabled.
Analog-to-Digital Converter (ADC)
SPRUH18I – JANUARY 2011 – REVISED JUNE 2022
TMS320x2806x Microcontrollers
543
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Summary of Contents for TMS320 2806 Series
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