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Texas Instruments TM4C1294NCPDT, Datasheet

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Table 9-8. Channel Control Word Configuration for Memory Transfer Example

Description

Value

Bits

Field in DMACHCTL

32-bit destination address increment

2

31:30

DSTINC

32-bit destination data size

2

29:28

DSTSIZE

32-bit source address increment

2

27:26

SRCINC

32-bit source data size

2

25:24

SRCSIZE

Reserved

0

23:22

reserved

Privileged access protection for
destination data writes

0

21

DSTPROT0

Reserved

0

20:19

reserved

Privileged access protection for source
data reads

0

18

SRCPROT0

Arbitrates after 8 transfers

3

17:14

ARBSIZE

Transfer 256 items

255

13:4

XFERSIZE

N/A for this transfer type

0

3

NXTUSEBURST

Use Auto-request transfer mode

2

2:0

XFERMODE

Configure Peripheral Interrupts

For memory-to-memory transfers, the peripheral involved must be configured to generate an interrupt
when the µDMA has completed its transfer. Upon completion, the µDMA will send a

dma_done

signal to the peripheral.

9.3.2.3

Start the Transfer

Now the channel is configured and is ready to start.

1.

Enable the channel by setting bit 30 of the

DMA Channel Enable Set (DMAENASET)

register.

2.

Issue a transfer request by setting bit 30 of the

DMA Channel Software Request (DMASWREQ)

register.

The μDMA transfer begins. If the interrupt is enabled, then the processor is notified by interrupt
when the transfer is complete. If needed, the status can be checked by reading bit 30 of the

DMAENASET

register. This bit is automatically cleared when the transfer is complete. The status

can also be checked by reading the

XFERMODE

field of the channel control word at offset 0x1E8.

This field is automatically cleared at the end of the transfer.

9.3.3

Configuring a Peripheral for Simple Transmit

This example configures the μDMA controller to transmit a buffer of data to a peripheral. The
peripheral has a transmit FIFO with a trigger level of 4. The example peripheral uses μDMA channel
7.

9.3.3.1

Configure the Channel Attributes

First, configure the channel attributes:

1.

Configure bit 7 of the

DMA Channel Priority Set (DMAPRIOSET)

or

DMA Channel Priority

Clear (DMAPRIOCLR)

registers to set the channel to High priority or Default priority.

2.

Set bit 7 of the

DMA Channel Primary Alternate Clear (DMAALTCLR)

register to select the

primary channel control structure for this transfer.

June 18, 2014

696

Texas Instruments-Production Data

Micro Direct Memory Access (μDMA)

Summary of Contents for TM4C1294NCPDT

Page 1: ...Tiva TM4C1294NCPDT Microcontroller DATA SHEET Copyright 2007 2014 Texas Instruments Incorporated DS TM4C1294NCPDT 15863 2743 SPMS433B TEXAS INSTRUMENTS PRODUCTION DATA...

Page 2: ...NOTICE Recipient agrees to not knowingly export or re export directly or indirectly any product or technical data as defined by the U S EU and other Export Administration Regulations including softwa...

Page 3: ...dware Details 78 1 5 Kits 79 1 6 Support Information 79 2 The Cortex M4F Processor 80 2 1 Block Diagram 81 2 2 Overview 82 2 2 1 System Level Interface 82 2 2 2 Integrated Configurable Debug 82 2 2 3...

Page 4: ...tection Unit MPU 137 3 1 5 Floating Point Unit FPU 142 3 2 Register Map 146 3 3 System Timer SysTick Register Descriptions 149 3 4 NVIC Register Descriptions 153 3 5 System Control Block SCB Register...

Page 5: ...ng Hibernate 546 7 3 11 Waking from Hibernate 546 7 3 12 Arbitrary Power Removal 547 7 3 13 Interrupts and Status 548 7 4 Initialization and Configuration 548 7 4 1 Initialization 548 7 4 2 RTC Match...

Page 6: ...Control Structure 702 9 6 DMA Register Descriptions 709 10 General Purpose Input Outputs GPIOs 742 10 1 Signal Description 743 10 2 Pad Capabilities 746 10 3 Functional Description 747 10 3 1 Data Con...

Page 7: ...ot Periodic Timer Mode 971 13 4 2 Real Time Clock RTC Mode 972 13 4 3 Input Edge Count Mode 972 13 4 4 Input Edge Time Mode 973 13 4 5 PWM Mode 973 13 5 Register Map 974 13 6 Register Descriptions 975...

Page 8: ...chronous Serial Interface QSSI 1226 17 1 Block Diagram 1226 17 2 Signal Description 1227 17 3 Functional Description 1228 17 3 1 Bit Rate Generation 1229 17 3 2 FIFO Operation 1229 17 3 3 Advanced Bi...

Page 9: ...3 11 Handling of Received Message Objects 1365 19 3 12 Handling of Interrupts 1367 19 3 13 Test Mode 1368 19 3 14 Bit Timing Configuration Error Considerations 1370 19 3 15 Bit Time and Bit Rate 1370...

Page 10: ...ctional Description 1672 23 3 1 Clock Configuration 1672 23 3 2 PWM Timer 1672 23 3 3 PWM Comparators 1673 23 3 4 PWM Signal Generator 1674 23 3 5 Dead Band Generator 1675 23 3 6 Interrupt ADC Trigger...

Page 11: ...ications 1838 27 9 6 System Clock Specification with ADC Operation 1842 27 9 7 System Clock Specification with USB Operation 1842 27 10 Sleep Modes 1843 27 11 Hibernation Module 1845 27 12 Flash Memor...

Page 12: ...7 Figure 7 3 Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON Mode 537 Figure 7 4 Using a Regulator for Both VDD and VBAT 538 Figure 7 5 Counter Behavior with a TRIM Value of 0...

Page 13: ...851 Figure 11 21 Read Accesses FRM50 0 FRMCNT 0 851 Figure 11 22 FRAME Signal Operation FRM50 0 and FRMCNT 0 852 Figure 11 23 FRAME Signal Operation FRM50 0 and FRMCNT 1 852 Figure 11 24 FRAME Signal...

Page 14: ...278 Figure 18 3 START and STOP Conditions 1279 Figure 18 4 Complete Data Transfer with a 7 Bit Address 1279 Figure 18 5 R S Bit in First Byte 1280 Figure 18 6 Data Validity During Bit Transfer on the...

Page 15: ...and Brown Out Assertions vs VDD Levels 1828 Figure 27 6 POK Assertion vs VDDC 1829 Figure 27 7 POR BOR VDD Glitch Response 1829 Figure 27 8 POR BOR VDD Droop Response 1830 Figure 27 9 Digital Power O...

Page 16: ...thernet 1871 Figure 27 35 Single Ended MOSC Characteristics for Ethernet 1872 Figure 27 36 Reset Timing 1872 Figure 27 37 100 Base TX Transmit Timing 1873 Figure 27 38 10Base TX Normal Link Pulse Timi...

Page 17: ...e 3 8 Peripherals Register Map 146 Table 3 9 Interrupt Priority Levels 171 Table 3 10 Example SIZE Field Values 199 Table 4 1 JTAG_SWD_SWO Signals 128TQFP 208 Table 4 2 JTAG Port Pins State after Powe...

Page 18: ...y 617 Table 8 5 Master Memory Access Availability 621 Table 8 6 Flash Register Map 622 Table 9 1 DMA Channel Assignments 680 Table 9 2 Request Type Support 682 Table 9 3 Control Structure Memory Map 6...

Page 19: ...er Map 949 Table 13 1 Available CCP Pins 956 Table 13 2 General Purpose Timers Signals 128TQFP 957 Table 13 3 General Purpose Timer Capabilities 958 Table 13 4 Counter Values When the Timer is Enabled...

Page 20: ...ansmit Descriptor 7 TDES7 1418 Table 20 8 Enhanced Receive Descriptor 0 RDES0 1419 Table 20 9 RDES0 Checksum Offload bits 1421 Table 20 10 Enhanced Receive Descriptor 1 RDES1 1422 Table 20 11 Enhanced...

Page 21: ...26 Table 27 14 Reset Characteristics 1831 Table 27 15 LDO Regulator Characteristics 1834 Table 27 16 Phase Locked Loop PLL Characteristics 1835 Table 27 17 System Divisor Factors for fvco 480 MHz 1836...

Page 22: ...rystal Specification 1871 Table 27 51 MOSC Single Ended 25 MHz Oscillator Specification a 1871 Table 27 52 Ethernet Controller Enable and Software Reset Timing 1872 Table 27 53 100Base TX Transmit Tim...

Page 23: ...offset 0x010 150 Register 2 SysTick Reload Value Register STRELOAD offset 0x014 152 Register 3 SysTick Current Value Register STCURRENT offset 0x018 153 Register 4 Interrupt 0 31 Set Enable EN0 offse...

Page 24: ...er 45 Interrupt 84 87 Priority PRI21 offset 0x454 161 Register 46 Interrupt 88 91 Priority PRI22 offset 0x458 161 Register 47 Interrupt 92 95 Priority PRI23 offset 0x45C 161 Register 48 Interrupt 96 9...

Page 25: ...71 Register 10 Main Oscillator Control MOSCCTL offset 0x07C 273 Register 11 Run and Sleep Mode Configuration Register RSCLKCFG offset 0x0B0 275 Register 12 Memory Timing Parameter Register 0 for Main...

Page 26: ...ral Present PPQEI offset 0x344 341 Register 56 Low Pin Count Interface Peripheral Present PPLPC offset 0x348 342 Register 57 Platform Environment Control Interface Peripheral Present PPPECI offset 0x3...

Page 27: ...igital Converter Run Mode Clock Gating Control RCGCADC offset 0x638 396 Register 100 Analog Comparator Run Mode Clock Gating Control RCGCACMP offset 0x63C 397 Register 101 Pulse Width Modulator Run Mo...

Page 28: ...0 439 Register 134 Universal Serial Bus Deep Sleep Mode Clock Gating Control DCGCUSB offset 0x828 441 Register 135 Ethernet PHY Deep Sleep Mode Clock Gating Control DCGCEPHY offset 0x830 442 Register...

Page 29: ...Register 174 Controller Area Network Peripheral Ready PRCAN offset 0xA34 514 Register 175 Analog to Digital Converter Peripheral Ready PRADC offset 0xA38 515 Register 176 Analog Comparator Peripheral...

Page 30: ...FC 596 Register 32 Hibernation Peripheral Properties HIBPP offset 0xFC0 598 Register 33 Hibernation Clock Control HIBCC offset 0xFC8 599 Internal Memory 600 Register 1 Flash Memory Address FMA offset...

Page 31: ...offset 0x22C 669 Register 48 Flash Memory Protection Read Enable 12 FMPRE12 offset 0x230 669 Register 49 Flash Memory Protection Read Enable 13 FMPRE13 offset 0x234 669 Register 50 Flash Memory Protec...

Page 32: ...ERRCLR offset 0x04C 727 Register 21 DMA Channel Assignment DMACHASGN offset 0x500 728 Register 22 DMA Channel Map Select 0 DMACHMAP0 offset 0x510 729 Register 23 DMA Channel Map Select 1 DMACHMAP1 off...

Page 33: ...805 Register 35 GPIO Peripheral Identification 7 GPIOPeriphID7 offset 0xFDC 806 Register 36 GPIO Peripheral Identification 0 GPIOPeriphID0 offset 0xFE0 807 Register 37 GPIO Peripheral Identification 1...

Page 34: ...Host Bus 16 Configuration 4 EPIHB16CFG4 offset 0x30C 925 Register 38 EPI Host Bus 8 Timing Extension EPIHB8TIME offset 0x310 929 Register 39 EPI Host Bus 16 Timing Extension EPIHB16TIME offset 0x310 9...

Page 35: ...Register 7 Watchdog Test WDTTEST offset 0x418 1039 Register 8 Watchdog Lock WDTLOCK offset 0xC00 1040 Register 9 Watchdog Peripheral Identification 4 WDTPeriphID4 offset 0xFD0 1041 Register 10 Watchd...

Page 36: ...1 ADC Sample Sequence Control 1 ADCSSCTL1 offset 0x064 1130 Register 32 ADC Sample Sequence Control 2 ADCSSCTL2 offset 0x084 1130 Register 33 ADC Sample Sequence 1 Operation ADCSSOP1 offset 0x070 1134...

Page 37: ...t Mask UARTIM offset 0x038 1194 Register 11 UART Raw Interrupt Status UARTRIS offset 0x03C 1198 Register 12 UART Masked Interrupt Status UARTMIS offset 0x040 1202 Register 13 UART Interrupt Clear UART...

Page 38: ...275 Register 1 I2 C Master Slave Address I2CMSA offset 0x000 1302 Register 2 I2 C Master Control Status I2CMCS offset 0x004 1303 Register 3 I2 C Master Data I2CMDR offset 0x008 1312 Register 4 I2 C Ma...

Page 39: ...MCTL offset 0x098 1399 Register 22 CAN IF1 Data A1 CANIF1DA1 offset 0x03C 1402 Register 23 CAN IF1 Data A2 CANIF1DA2 offset 0x040 1402 Register 24 CAN IF1 Data B1 CANIF1DB1 offset 0x044 1402 Register...

Page 40: ...ted after Single Collision EMACTXCNTSCOL offset 0x14C 1524 Register 30 Ethernet MAC Transmit Frame Count for Frames Transmitted after Multiple Collisions EMACTXCNTMCOL offset 0x150 1525 Register 31 Et...

Page 41: ...er 72 Ethernet PHY Basic Mode Control MR0 EPHYBMCR address 0x000 1590 Register 73 Ethernet PHY Basic Mode Status MR1 EPHYBMSR address 0x001 1592 Register 74 Ethernet PHY Identifier Register 1 MR2 EPHY...

Page 42: ...er 5 PWM Output Fault PWMFAULT offset 0x010 1690 Register 6 PWM Interrupt Enable PWMINTEN offset 0x014 1692 Register 7 PWM Raw Interrupt Status PWMRIS offset 0x018 1694 Register 8 PWM Interrupt Status...

Page 43: ...gister 56 PWM0 Dead Band Rising Edge Delay PWM0DBRISE offset 0x06C 1731 Register 57 PWM1 Dead Band Rising Edge Delay PWM1DBRISE offset 0x0AC 1731 Register 58 PWM2 Dead Band Rising Edge Delay PWM2DBRIS...

Page 44: ...operties PWMPP offset 0xFC0 1745 Register 89 PWM Clock Configuration PWMCC offset 0xFC8 1747 Quadrature Encoder Interface QEI 1748 Register 1 QEI Control QEICTL offset 0x000 1755 Register 2 QEI Status...

Page 45: ...oved Orderable Part Numbers table to addendum Deleted Packaging Materials section and put into separate packaging document Additional minor data sheet clarifications and corrections 15802 2729 April 2...

Page 46: ...lay parameter In EPI PSRAM Interface Characteristics table updated Min value for EPI_CLK period In ADC Electrical Characteristics at 1 Msps table updated values for VADCIN parameter Corrected ADC Inpu...

Page 47: ...ues Added EEPROM initialization code to EEPROM Initialization and Configuration section In the ADC chapter Added section Sample and Hold Window Control and clarified section Sample Phase Control Clari...

Page 48: ...300 TivaWare for C Series Release Notes literature number SPMU299 TivaWare Peripheral Driver Library for C Series User s Guide literature number SPMU298 TivaWare USB Library for C Series User s Guide...

Page 49: ...ading the bit field RC Software can read this field Always write the chip reset value RO Software can read or write this field RW Software can read or write this field Writing to it with any value cle...

Page 50: ...o drive it Low to deassert SIGNAL is to drive it High SIGNAL Signal names are in uppercase and in the Courier font An active High signal has no overbar To assert SIGNAL is to drive it High to deassert...

Page 51: ...Information on page 79 1 1 Tiva C Series Overview The Tiva C Series ARM Cortex M4 microcontrollers provide top performance and advanced integration The product family is positioned for cost effective...

Page 52: ...re Internal ROM 8 16 32 bit dedicated interface for peripherals and memory External Peripheral Interface EPI Security 16 32 bit Hash function that supports four CRC forms Cyclical Redundancy Check CRC...

Page 53: ...ntegrated ARM SWD JTAG and Serial Wire Debug SWD Package Information 128 pin TQFP Package Industrial 40 C to 85 C temperature range Extended 40 C to 105 C temperature range Operating Range Ambient Fig...

Page 54: ...mer 2 Units DMA Hibernation Module Tamper EEPROM 6K General Purpose Timer 8 Units GPIOs 90 External Peripheral Interface CRC Module SERIAL PERIPHERALS UART 8 Units USB OTG FS PHY or ULPI I2C 10 Units...

Page 55: ...d 16 bit devices typically in the range of a few kilobytes of memory for microcontroller class applications Single cycle multiply instruction and hardware divide Atomic bit manipulation bit banding de...

Page 56: ...state is automatically stored to the stack on an exception and automatically restored from the stack at the end of the Interrupt Service Routine ISR The interrupt vector is fetched in parallel to the...

Page 57: ...l ROM loaded with TivaWare for C Series software TivaWare Peripheral Driver Library TivaWare Boot Loader Advanced Encryption Standard AES cryptography tables Cyclic Redundancy Check CRC error detectio...

Page 58: ...mance of the ARM Cortex M4F core No special pragmas or custom assembly code prologue epilogue functions are required For applications that require in field programmability the royalty free TivaWare Bo...

Page 59: ...for external peripherals and memory Memory interface supports contiguous memory access independent of data bus width thus enabling code execution directly from SDRAM SRAM and Flash memory Blocking and...

Page 60: ...address FIFO x8 and x16 interface variant with support for external FIFO XFIFO EMPTY and FULL signals Speed controlled with read and write data wait state counters Support for read write burst mode to...

Page 61: ...hardware and both Media Independent Interface MII and Reduced MII RMII support integrated PHY provided Two CAN 2 0 A B controllers USB 2 0 Controller OTG Host Device with optional high speed using ex...

Page 62: ...ode support Processor offloading Programmable insertion TX or deletion RX of preamble and start of frame data Programmable generation TX or deletion RX of CRC and pad data IP header and hardware check...

Page 63: ...le Automatic Retransmission mode for Time Triggered CAN TTCAN applications Programmable loopback mode for self test operation Programmable FIFO mode enables storage of multiple message objects Glueles...

Page 64: ...though the functionality is similar to a 16C550 UART this UART design is not register compatible The UART can generate individually masked interrupts from the Rx Tx modem flow control modem status and...

Page 65: ...urst request asserted at programmed FIFO level Global Alternate Clock ALTCLK resource or System Clock SYSCLK can be used to generate baud clock 1 3 5 5 I2 C see page 1275 The Inter Integrated Circuit...

Page 66: ...capability Master and slave interrupt generation Master generates interrupts when a transmit or receive operation completes or aborts due to an error Slave generates interrupts when data has been tran...

Page 67: ...interfaces in Legacy Mode Support for Freescale interface in Bi and Quad SSI mode Master or slave operation Programmable clock bit rate and prescaler Separate transmit and receive FIFOs each 16 bits w...

Page 68: ...and peripherals It has dedicated channels for each supported on chip module and can be programmed to automatically perform transfers between peripherals and memory as the peripheral is ready to transf...

Page 69: ...e digital logic and analog circuits Low power options for microcontroller Sleep and Deep Sleep modes with clock gating Low power options for on chip modules software controls shutdown of individual pe...

Page 70: ...e configured to operate independently as timers or event counters or configured to operate as one 32 bit timer or one 32 bit Real Time Clock RTC Timers can also be used to trigger analog to digital AD...

Page 71: ...es Capture The GP Timer is incremented decremented by programmed events on the CCP input The GP Timer captures and stores the current timer value when a programmed event occurs Compare The GP Timer is...

Page 72: ...litch filter Configurable tamper event response Logging of up to four tamper events Optional BBRAM erase on tamper detection Tamper wake from hibernate capability Hibernation clock input failure detec...

Page 73: ...ion from runaway software Reset generation logic with an enable disable User enabled stalling when the microcontroller asserts the CPU Halt flag during debug 1 3 6 7 Programmable GPIOs see page 742 Ge...

Page 74: ...PWM see page 1669 The TM4C1294NCPDT microcontroller contains one PWM module with four PWM generator blocks and a control block for a total of 8 PWM outputs Pulse width modulation PWM is a powerful te...

Page 75: ...output inversion of each PWM signal polarity control Optional fault handling for each PWM signal Synchronization of timers in the PWM generator blocks Synchronization of timer comparator updates acros...

Page 76: ...ch with a sample rate of two million samples second Three analog comparators On chip voltage regulator The following provides more detail on these analog functions 1 3 8 1 ADC see page 1053 An analog...

Page 77: ...rs see page 1653 An analog comparator is a peripheral that compares two analog voltages and provides a logical output that signals the comparison result The TM4C1294NCPDT microcontroller provides thre...

Page 78: ...AG debug and test functionality plus real time access to system memory without halting the core or requiring any target resident code The SWJ DP interface has the following features IEEE 1149 1 1990 c...

Page 79: ...are design files Evaluation Kits provide a low cost and effective means of evaluating TM4C1294NCPDT microcontrollers before purchase Development Kits provide you with all the tools you need to develop...

Page 80: ...ss enabling data to be efficiently packed into memory IEEE754 compliant single precision Floating Point Unit FPU 16 bit SIMD vector processing unit Fast code execution permits slower processor clock o...

Page 81: ...and multiply with accumulate capabilities saturating arithmetic and dedicated hardware division To facilitate the design of cost sensitive devices the Cortex M4F processor implements tightly coupled s...

Page 82: ...pplications to implement security privilege levels and separate code data and stack on a task by task basis 2 2 2 Integrated Configurable Debug The Cortex M4F processor implements a complete hardware...

Page 83: ...ccesses are redirected to a remap table specified in the FPB configuration For more information on the Cortex M4F debug capabilities see theARM Debug Interface V5 Architecture Specification 2 2 3 Trac...

Page 84: ...bes the Cortex M4F programming model In addition to the individual core register descriptions information about the processor modes and privilege levels for software execution and stacks is included 2...

Page 85: ...e 89 In Thread mode the CONTROL register see page 99 controls whether the processor uses the main stack or the process stack In Handler mode the processor always uses the main stack The options for pr...

Page 86: ...pe Name Offset 88 Cortex General Purpose Register 0 RW R0 88 Cortex General Purpose Register 1 RW R1 88 Cortex General Purpose Register 2 RW R2 88 Cortex General Purpose Register 3 RW R3 88 Cortex Gen...

Page 87: ...Register 0x0000 0000 RW BASEPRI 99 Control Register 0x0000 0000 RW CONTROL 101 Floating Point Status Control RW FPSC 2 3 4 Register Descriptions This section lists and describes the Cortex M4F registe...

Page 88: ...r 11 Cortex General Purpose Register 10 R10 Register 12 Cortex General Purpose Register 11 R11 Register 13 Cortex General Purpose Register 12 R12 The Rn registers are 32 bit general purpose registers...

Page 89: ...e MSP with the value from address 0x0000 0000 The MSP can only be accessed in privileged mode the PSP can be accessed in either privileged or unprivileged mode Stack Pointer SP Type RW reset 16 17 18...

Page 90: ...values and description Link Register LR Type RW reset 0xFFFF FFFF 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 LINK RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 1 1 1 1 1 1 1 1 1 1 1 1 1 1...

Page 91: ...t be 1 The PC register can be accessed in either privileged or unprivileged mode Program Counter PC Type RW reset 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 PC RW RW RW RW RW RW RW RW RW RW RW RW...

Page 92: ...of the current Interrupt Service Routine ISR These registers can be accessed individually or as a combination of any two or all three registers using the register name as an argument to the MSR or MRS...

Page 93: ...e previous add operation did not result in a carry bit or the previous subtract operation resulted in a borrow bit 0 The value of this bit is only meaningful when accessing PSR or APSR 0 RW C 29 APSR...

Page 94: ...ithin an exception handler 0x0 RO ICI IT 26 25 EPSR Thumb State This bit indicates the Thumb state and should always be set The following can clear the THUMB bit The BLX BX and POP PC instructions Res...

Page 95: ...all the same or some can be the inverse of others See the Cortex M4 instruction set chapter in the ARM Cortex M4 Devices Generic User Guide literature number ARM DUI 0553A for more information The va...

Page 96: ...formation on exception priority levels see Exception Types on page 114 Priority Mask Register PRIMASK Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO...

Page 97: ...egister FAULTMASK Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3...

Page 98: ...ompatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x0000 00 RO reserved 31 8 Base Priority Any exception that has a programmable pr...

Page 99: ...uction immediately after the MSR instruction ensuring that instructions after the ISB execute use the new stack pointer See the Cortex M4 instruction set chapter in the ARM Cortex M4 Devices Generic U...

Page 100: ...de this bit reads as zero and ignores writes The Cortex M4F updates this bit automatically on exception return 0 RW ASP 1 Thread Mode Privilege Level Description Value Unprivileged software can be exe...

Page 101: ...int comparison operations update this condition code flag RW V 28 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit shou...

Page 102: ...Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x0 RO reserv...

Page 103: ...n page 103 In this manual register addresses are given as a hexadecimal increment relative to the module s base address as shown in the memory map The regions for SRAM and peripherals include bit band...

Page 104: ...9 I2 C 1 0x4002 1FFF 0x4002 1000 1299 I2 C 2 0x4002 2FFF 0x4002 2000 1299 I2 C 3 0x4002 3FFF 0x4002 3000 755 GPIO Port E 0x4002 4FFF 0x4002 4000 755 GPIO Port F 0x4002 5FFF 0x4002 5000 755 GPIO Port G...

Page 105: ...GPIO Port L AHB aperture 0x4006 2FFF 0x4006 2000 755 GPIO Port M AHB aperture 0x4006 3FFF 0x4006 3000 755 GPIO Port N AHB aperture 0x4006 4FFF 0x4006 4000 755 GPIO Port P AHB aperture 0x4006 5FFF 0x40...

Page 106: ...Watchpoint and Trace DWT 0xE000 1FFF 0xE000 1000 82 Flash Patch and Breakpoint FPB 0xE000 2FFF 0xE000 2000 Reserved 0xE000 DFFF 0xE000 3000 146 Cortex M4F Peripherals SysTick NVIC MPU FPU and SCB 0xE...

Page 107: ...e information on memory types and the XN attribute Tiva C Series devices may have reserved memory areas within the address ranges shown below refer to Table 2 4 on page 103 for more information Table...

Page 108: ...rier ISB instruction ensures that the effect of all completed memory transactions is recognizable by subsequent instructions Memory barrier instructions can be used in the following situations MPU pro...

Page 109: ...nd alias region maps to a single bit in the SRAM or peripheral bit band region A word access to a bit band address results in a word access to the underlying memory and similarly for halfword and byte...

Page 110: ...examples of bit band mapping between the SRAM bit band alias region and the SRAM bit band region The alias word at 0x23FF FFE0 maps to bit 0 of the bit band byte at 0x200F FFFF 0x23FF FFE0 0x2200 000...

Page 111: ...Bits 31 1 of the alias word have no effect on the bit band bit Writing 0x01 has the same effect as writing 0xFF Writing 0x00 has the same effect as writing 0x0E When reading a word in the alias regio...

Page 112: ...on which is used to attempt to write to the same memory location and returns a status bit to a register If this status bit is clear it indicates that the thread or process gained exclusive access to t...

Page 113: ...ler NVIC prioritize and handle all exceptions in Handler Mode The processor state is automatically stored to the stack on an exception and automatically restored from the stack at the end of the Inter...

Page 114: ...n When reset is deasserted execution restarts from the address provided by the reset entry in the vector table Execution restarts as privileged execution in Thread mode NMI A non maskable Interrupt NM...

Page 115: ...rupt Control and State INTCTRL register In an OS environment the processor can use this exception as system tick Interrupt IRQ An interrupt or IRQ is an exception signaled by a peripheral or generated...

Page 116: ...9 Table 2 9 Interrupts Description Vector Address or Offset Interrupt Number Bit in Interrupt Registers Vector Number Processor exceptions 0x0000 0000 0x0000 003C 0 15 GPIO Port A 0x0000 0040 0 16 GPI...

Page 117: ...0 00D0 36 52 I2 C1 0x0000 00D4 37 53 CAN 0 0x0000 00D8 38 54 CAN1 0x0000 00DC 39 55 Ethernet MAC 0x0000 00E0 40 56 HIB 0x0000 00E4 41 57 USB MAC 0x0000 00E8 42 58 PWM Generator 3 0x0000 00EC 43 59 uDM...

Page 118: ...Port P4 0x0000 0180 80 96 GPIO Port P5 0x0000 0184 81 97 GPIO Port P6 0x0000 0188 82 98 GPIO Port P7 0x0000 018C 83 99 GPIO Port Q Summary or Q0 0x0000 0190 84 100 GPIO Port Q1 0x0000 0194 85 101 GPIO...

Page 119: ...page 119 shows the order of the exception vectors in the vector table The least significant bit of each vector must be 1 indicating that the exception handler is Thumb code Figure 2 6 Vector Table In...

Page 120: ...rity as the exception being handled the handler is not preempted irrespective of the exception number However the status of the new interrupt changes to pending 2 5 6 Interrupt Priority Grouping To in...

Page 121: ...tail chaining rules apply 2 5 7 1 Exception Entry Exception entry occurs when there is a pending exception with sufficient priority and either the processor is in Thread mode or the new exception is o...

Page 122: ...s from the vector table When stacking is complete the processor starts executing the exception handler At the same time the processor writes an EXC_RETURN value to the LR indicating which stack pointe...

Page 123: ...F FFE1 Reserved 0xFFFF FFE2 0xFFFF FFE8 Return to Thread mode Exception return uses floating point state from MSP Execution uses MSP after return 0xFFFF FFE9 Reserved 0xFFFF FFEA 0xFFFF FFEC Return to...

Page 124: ...default memory mismatch during lazy floating point state preservation BSTKE Bus Fault Status BFAULTSTAT Bus fault Bus error during exception stacking BUSTKE Bus Fault Status BFAULTSTAT Bus fault Bus e...

Page 125: ...gh the stack push for the handler failed The fault handler operates but the stack contents are corrupted Note Only Reset and NMI can preempt the fixed priority hard fault A hard fault can preempt any...

Page 126: ...de See the Cortex M4 instruction set chapter in the ARM Cortex M4 Devices Generic User Guide literature number ARM DUI 0553A for more information 2 7 1 2 Wait for Event The wait for event instruction...

Page 127: ...CTRL see page 173 2 8 Instruction Set Summary The processor implements a version of the Thumb instruction set Table 2 13 on page 127 lists the supported instructions Note In Table 2 13 on page 127 Ang...

Page 128: ...Rt Rt2 Rn offset LDRD Load register exclusive Rt Rn offset LDREX Load register exclusive with byte Rt Rn LDREXB Load register exclusive with halfword Rt Rn LDREXH Load register with halfword Rt Rn off...

Page 129: ...rd Rd Rn REV Reverse byte order in each halfword Rd Rn REV16 Reverse byte order in bottom halfword and sign extend Rd Rn REVSH N Z C Rotate right Rd Rm Rs n ROR RORS N Z C Rotate right with extend Rd...

Page 130: ...RdLo RdHi Rn Rm SMLSLD SMLSLDX Signed most significant word multiply accumulate Rd Rn Rm Ra SMMLA Signed most significant word multiply subtract Rd Rn Rm Ra SMMLS SMMLR Signed most significant word mu...

Page 131: ...d Rn Rm ROR SXTAB Dual extend 8 bits to 16 and add Rd Rn Rm ROR SXTAB16 Extend 16 bits to 32 and add Rd Rn Rm ROR SXTAH Signed extend byte 16 Rd Rm ROR n SXTB16 Sign extend a byte Rd Rm ROR n SXTB Sig...

Page 132: ...and Add Rd Rn Rm ROR UXTAB Rotate dual extend 8 bits to 16 and Add Rd Rn Rm ROR UXTAB16 Rotate unsigned extend and Add Halfword Rd Rn Rm ROR UXTAH Zero extend a Byte Rd Rm ROR n UXTB Unsigned Extend...

Page 133: ...gle precision Sm Sm1 Rt Rt2 VMOV Copy ARM core register to scalar Dd x Rt VMOV Copy scalar to ARM core register Rt Dn x VMOV N Z C V Move FPSCR to ARM core register or APSR Rt FPSCR VMRS FPSCR Move to...

Page 134: ...Floating Point Unit FPU see page 142 Fully supports single precision add subtract multiply divide multiply and accumulate and square root operations It also provides conversions between fixed point an...

Page 135: ...vide the counter s wrap value SysTick Current Value STCURRENT The current value of the counter When enabled the timer counts down on each clock from the reload value to zero reloads wraps to the value...

Page 136: ...led synchronously on the rising edge of the processor clock To ensure the NVIC detects the interrupt the peripheral must assert the interrupt signal for at least one clock cycle during which the NVIC...

Page 137: ...reporting of the system exceptions 3 1 4 Memory Protection Unit MPU This section describes the Memory protection unit MPU The MPU divides the memory map into a number of regions and defines the locat...

Page 138: ...en programmed disable unused regions to prevent any previous region settings from affecting the new MPU setup 3 1 4 1 Updating an MPU Region To update the attributes for an MPU region the MPU Region N...

Page 139: ...quired after changing MPU settings such as at the end of context switch An ISB is required if the code that programs the MPU region or regions is entered using a branch or call If the programming sequ...

Page 140: ...ion one apply to the first 128 KB region configure the SRD field for region two to 0x03 to disable the first two subregions as Figure 3 1 on page 140 shows Figure 3 1 SRD Use Example Region 1 Disabled...

Page 141: ...ignores the value of this bit Table 3 4 on page 141 shows the cache policy for memory attribute encodings with a TEX value in the range of 0x4 0x7 Table 3 4 Cache Policy for Memory Attribute Encoding...

Page 142: ...ault see Exceptions and Interrupts on page 103 for more information The MFAULTSTAT register indicates the cause of the fault See page 184 for more information 3 1 5 Floating Point Unit FPU This sectio...

Page 143: ...hardware Flush to Zero mode Setting the FZ bit of the Floating Point Status and Control FPSC register enables Flush to Zero mode In this mode the FPU treats all subnormal input operands of arithmetic...

Page 144: ...ith the maximum exponent field value and a nonzero fraction field are valid NaNs A most significant fraction bit of zero indicates a Signaling NaN SNaN A one indicates a Quiet NaN QNaN Two NaN values...

Page 145: ...SCR 3 is set See the ARM Architecture Reference Manual for information on flush to zero mode When the FPU is not in flush to zero mode operations are performed on subnormal operands If the operation d...

Page 146: ...et System Timer SysTick Registers 150 SysTick Control and Status Register 0x0000 0000 RW STCTRL 0x010 152 SysTick Reload Value Register RW STRELOAD 0x014 153 SysTick Current Value Register RWC STCURRE...

Page 147: ...5 0x414 159 Interrupt 24 27 Priority 0x0000 0000 RW PRI6 0x418 159 Interrupt 28 31 Priority 0x0000 0000 RW PRI7 0x41C 159 Interrupt 32 35 Priority 0x0000 0000 RW PRI8 0x420 159 Interrupt 36 39 Priorit...

Page 148: ...ty 1 0x0000 0000 RW SYSPRI1 0xD18 178 System Handler Priority 2 0x0000 0000 RW SYSPRI2 0xD1C 179 System Handler Priority 3 0x0000 0000 RW SYSPRI3 0xD20 180 System Handler Control and State 0x0000 0000...

Page 149: ...2 Coprocessor Access Control 0x0000 0000 RW CPAC 0xD88 203 Floating Point Context Control 0xC000 0000 RW FPCC 0xF34 205 Floating Point Context Address RW FPCA 0xF38 206 Floating Point Default Status C...

Page 150: ...ite operation 0x000 RO reserved 31 17 Count Flag Description Value The SysTick timer has not counted to 0 since the last time this bit was read 0 The SysTick timer has counted to 0 since the last time...

Page 151: ...ts to 0 1 0 RW INTEN 1 Enable Description Value The counter is disabled 0 Enables SysTick to operate in a multi shot way That is the counter loads the RELOAD value and begins counting down On reaching...

Page 152: ...n order to access this register correctly the system clock must be faster than 8 MHz SysTick Reload Value Register STRELOAD Base 0xE000 E000 Offset 0x014 Type RW reset 16 17 18 19 20 21 22 23 24 25 26...

Page 153: ...er is accessed No read modify write protection is provided so change with care This register is write clear Writing to it with any value clears the register Clearing this register also clears the COUN...

Page 154: ...nterrupt based on its priority If an interrupt is not enabled asserting its interrupt signal changes the interrupt state to pending but the NVIC never activates the interrupt regardless of its priorit...

Page 155: ...See Table 2 9 on page 116 for interrupt assignments Interrupt 0 31 Clear Enable DIS0 Base 0xE000 E000 Offset 0x180 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 INT RW RW R...

Page 156: ...interrupt assignments Interrupt 0 31 Set Pending PEND0 Base 0xE000 E000 Offset 0x200 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 INT RW RW RW RW RW RW RW RW RW RW RW RW R...

Page 157: ...113 See Table 2 9 on page 116 for interrupt assignments Interrupt 0 31 Clear Pending UNPEND0 Base 0xE000 E000 Offset 0x280 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 INT...

Page 158: ...rresponds to Interrupt 96 bit 17 corresponds to Interrupt 113 See Table 2 9 on page 116 for interrupt assignments Caution Do not manually set or clear the bits in this register Interrupt 0 31 Active B...

Page 159: ...ter 38 Interrupt 56 59 Priority PRI14 offset 0x438 Register 39 Interrupt 60 63 Priority PRI15 offset 0x43C Note This register can only be accessed from privileged mode The PRIn registers see also page...

Page 160: ...e value the greater the priority of the corresponding interrupt 0x0 RW INTC 23 21 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a r...

Page 161: ...ter can only be accessed from privileged mode The PRIn registers see also page 159 provide 3 bit priority fields for each interrupt These registers are byte accessible Each register holds four priorit...

Page 162: ...the value the greater the priority of the corresponding interrupt 0x0 RW INTC 23 21 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a...

Page 163: ...0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should...

Page 164: ...rved across a read modify write operation 0x00 RO reserved 31 10 Disable Out Of Order Floating Point Disables floating point instructions completing out of order with respect to integer instructions 0...

Page 165: ...te This bit only affects write buffers implemented in the Cortex M4 processor 0 RW DISWBUF 1 Disable Interrupts of Multiple Cycle Instructions Description Value No effect 0 Disables interruption of lo...

Page 166: ...ARTNO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 0 0 0 0 0 1 0 0 1 0 0 0 0 1 1 Reset Description Reset Type Name Bit Field Implementer Code Description Value ARM 0x41 0x41 RO IMP 31 24 Var...

Page 167: ...pe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field NMI Set Pending Description Value On a read indicates an NMI exception is not pending On a write no effect 0 On a read in...

Page 168: ...nown 0 WO PENDSTCLR 25 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write...

Page 169: ...status for all interrupts excluding NMI and Faults This bit only has meaning if the processor is currently executing an ISR the Interrupt Program Status IPSR register is non zero 0 RO RETBASE 11 Softw...

Page 170: ...3 14 15 reserved OFFSET RO RO RO RO RO RO RO RO RO RO RW RW RW RW RW RW Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Vector Table Offset When configuring the OFFSET...

Page 171: ...6 bxx y 0x5 4 2 6 5 7 bx yy 0x6 8 1 7 5 None b yyy 0x7 a INTx field showing the binary point An x denotes a group priority field bit and a y denotes a subpriority field bit Application Interrupt and...

Page 172: ...7 3 System Reset Request Description Value No effect 0 Resets the core and all on chip peripherals except the Debug interface 1 This bit is automatically cleared during the reset of the core and read...

Page 173: ...read modify write operation 0x0000 00 RO reserved 31 5 Wake Up on Pending Description Value Only enabled interrupts or events can wake up the processor disabled interrupts are excluded 0 Enabled even...

Page 174: ...eep sleep on return from an ISR 1 Setting this bit enables an interrupt driven application to avoid returning to an empty main application 0 RW SLEEPEXIT 1 Software should not rely on the value of a r...

Page 175: ...tion 0x0000 00 RO reserved 31 10 Stack Alignment on Exception Entry Description Value The stack is 4 byte aligned 0 The stack is 8 byte aligned 1 On exception entry the processor uses bit 9 of the sta...

Page 176: ...s set 0 RW UNALIGNED 3 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write...

Page 177: ...ult Configurable priority values are in the range 0 7 with lower values having higher priority 0x0 RW USAGE 23 21 Software should not rely on the value of a reserved bit To provide compatibility with...

Page 178: ...0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field SVCall...

Page 179: ...y 0x0 RW TICK 31 29 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write ope...

Page 180: ...st be modified after enabling the system handlers a read modify write procedure must be used to ensure that only the required bit is modified System Handler Control and State SYSHNDCTRL Base 0xE000 E0...

Page 181: ...Management Fault Pending Description Value A memory management fault exception is not pending 0 A memory management fault exception is pending 1 This bit can be modified to change the pending status o...

Page 182: ...above before setting this bit 0 RW SVCA 7 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a...

Page 183: ...fault is not active 0 Memory management fault is active 1 This bit can be modified to change the active status of the memory management fault exception however see the Caution above before setting th...

Page 184: ...the BFARV bit in BFAULTSTAT to determine if the MMADDR or FAULTADDR contents are valid Software must follow this sequence because another higher priority exception might change the MMADDR or FAULTADDR...

Page 185: ...NALIGNED bit in the CFGCTRL register see page 175 This bit is cleared by writing a 1 to it 0 RW1C UNALIGN 24 Software should not rely on the value of a reserved bit To provide compatibility with futur...

Page 186: ...s Register Valid Description Value The value in the Bus Fault Address FAULTADDR register is not a valid fault address 0 The FAULTADDR register is holding a valid fault address 1 This bit is set after...

Page 187: ...rror has not occurred 0 A data bus error has occurred but the return address in the stack frame is not related to the instruction that caused the error 1 When this bit is set a fault address is not wr...

Page 188: ...register value has been overwritten This bit is cleared by writing a 1 to it 0 RW1C MMARV 7 Software should not rely on the value of a reserved bit To provide compatibility with future products the v...

Page 189: ...n Value A data access violation has not occurred 0 The processor attempted a load or store at a location that does not permit the operation 1 When this bit is set the PC value stacked for the exceptio...

Page 190: ...ault with configurable priority that cannot be handled either because of priority or because it is disabled 1 When this bit is set the hard fault handler must read the other fault status registers to...

Page 191: ...gement Fault Status MFAULTSTAT register indicate the cause of the fault and whether the value in the MMADDR register is valid see page 184 Memory Management Fault Address MMADDR Base 0xE000 E000 Offse...

Page 192: ...e 0xE000 E000 Offset 0xD38 Type RW reset 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ADDR RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ADDR RW R...

Page 193: ...ed bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x00 RO reserved 31 24 Number of I Regions This field indicate...

Page 194: ...s if the MPU is not implemented see Table 2 5 on page 107 for more information The default memory map applies to accesses from both privileged and unprivileged software When the MPU is enabled accesse...

Page 195: ...his default map If the MPU is disabled the processor ignores this bit 0 RW PRIVDEFEN 2 MPU Enabled During Faults This bit controls the operation of the MPU during hard fault NMI and FAULTMASK handlers...

Page 196: ...D98 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10...

Page 197: ...case the region occupies the complete memory map and the base address is 0x0000 0000 The base address is aligned to the size of the region For example a 64 KB region must be aligned on a multiple of...

Page 198: ...updated for the region specified in the REGION field 1 This bit is always read as 0 0 WO VALID 4 Software should not rely on the value of a reserved bit To provide compatibility with future products t...

Page 199: ...ze of the MPU memory region specified by the MPUNUMBER register as follows Region size in bytes 2 SIZE 1 The smallest permitted region size is 32 bytes corresponding to a SIZE value of 4 Table 3 10 on...

Page 200: ...on on using this bit field see Table 3 3 on page 140 0x0 RW TEX 21 19 Shareable For information on using this bit see Table 3 3 on page 140 0 RW S 18 Cacheable For information on using this bit see Ta...

Page 201: ...bled 0 The region is enabled 1 0 RW ENABLE 0 3 7 Floating Point Unit FPU Register Descriptions This section lists and describes the Floating Point Unit FPU registers in numerical order by address offs...

Page 202: ...cross a read modify write operation 0x00 RO reserved 31 24 CP11 Coprocessor Access Privilege Description Value Access Denied Any attempted access generates a NOCP Usage Fault 0x0 Privileged Access Onl...

Page 203: ...A bit in the Auxiliary Control ACTLR register 1 RW ASPEN 31 Lazy State Preservation Enable When set enables automatic lazy state preservation for floating point context 1 RW LSPEN 30 Software should n...

Page 204: ...value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 RO reserved 2 User Privilege Level When set...

Page 205: ...t 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved ADDRESS RO RO RO RW RW RW RW RW RW RW RW RW RW RW RW RW Type 0 0 0 Reset Description Reset Type Name Bit Field Address The location of the unpopulated...

Page 206: ...erved bit should be preserved across a read modify write operation 0x00 RO reserved 31 27 AHP Bit Default This bit holds the default value for the AHP bit in the FPSC register RW AHP 26 DN Bit Default...

Page 207: ...nto the Cortex M4F core by multiplexing the TDO outputs from both JTAG controllers ARM JTAG instructions select the ARM TDO output while JTAG instructions select the TDO output The multiplexer is cont...

Page 208: ...ux Pin Assignment lists the GPIO pin placement for the JTAG SWD controller signals The AFSEL bit in the GPIO Alternate Function Select GPIOAFSEL register page 770 is set to choose the JTAG SWD functio...

Page 209: ...instructions like EXTEST operate on data currently in a DR chain and do not capture shift or update any of the chains Instructions that are not implemented decode to the BYPASS instruction to ensure...

Page 210: ...e JTAG TAP controller TMS is sampled on the rising edge of TCK Depending on the current TAP state and the sampled value of TMS the next state may be entered Because the TMS pin is sampled on the risin...

Page 211: ...tates see page 776 and page 778 Note If the device fails initialization during reset the hardware toggles the TDO output as an indication of failure Thus during board layout designers should not desig...

Page 212: ...the shift registers is discussed in detail in Register Descriptions on page 215 4 3 4 Operational Considerations Certain operational parameters must be considered when using the JTAG module Because th...

Page 213: ...d GPIO Digital Enable GPIODEN register see page 781 are not committed to storage unless the GPIO Lock GPIOLOCK register see page 783 has been unlocked and the appropriate bits of the GPIO Commit GPIOC...

Page 214: ...st Logic Reset state From here the preamble sequences the TAP controller through the following states Run Test Idle Select DR Select IR Test Logic Reset Test Logic Reset Run Test Idle Run Test Idle Se...

Page 215: ...WCLK cycles with TMS SWDIO High to ensure that if SWJ DP was already in JTAG mode before sending the switch sequence the JTAG goes into the Test Logic Reset state To verify that the Debug Access Port...

Page 216: ...data in the Boundary Scan Data Register associated with the outputs and output enables are used to drive the GPIO pads rather than the signals coming from the core With tests that drive known values o...

Page 217: ...version of the ARM core This information can be used by testing equipment and debuggers to automatically configure input and output data streams IDCODE is the default instruction loaded into the JTAG...

Page 218: ...undary Scan Data Register is shown in Figure 4 5 Each GPIO pin starting with a GPIO pin next to the JTAG port pins is included in the Boundary Scan Data Register Each GPIO pin has three associated dig...

Page 219: ...in the ARM Debug Interface V5 Architecture Specification 4 5 2 6 ABORT Data Register The format for the 35 bit ABORT Data Register defined by ARM is described in the ARM Debug Interface V5 Architectur...

Page 220: ...d in the Pin Mux Pin Assignment column have a fixed pin assignment and function Table 5 1 System Control Clocks Signals 128TQFP Description Buffer Type Pin Type Pin Mux Pin Assignment Pin Number Pin N...

Page 221: ...t with the software reset registers see page 226 5 A watchdog timer reset condition violation see page 226 6 Hibernation module event 7 A software restart initiated through a Hardware System Service R...

Page 222: ...check of the Flash at address 0x0000 0004 contains a valid reset vector value and the BOOTCFG register does not indicate the boot loader the boot sequence causes the stack pointer reset vector fetch f...

Page 223: ...utes a full initialization of the device Upon completion the core loads from memory the initial stack pointer the initial program counter and the first instruction designated by the program counter an...

Page 224: ...controller Note Typical RPU 10 k Typical RS 470 C1 10 nF 5 2 2 5 Brown Out Reset BOR The microcontroller provides a brown out detection circuit that triggers if the VDD external or VDDA analog power s...

Page 225: ...n the Reset Cause RESC register System Control offset 0x05C This bit is set only if either of the BOR events have been configured to initiate a reset See page 267 In addition the following bits contro...

Page 226: ...al reset is asserted 3 The internal reset is deasserted and the microcontroller loads from memory the initial stack pointer the initial program counter and the first instruction designated by the prog...

Page 227: ...being serviced 2 An internal reset is asserted 3 The internal reset is released and the microcontroller loads from memory the initial stack pointer the initial program counter and the first instructi...

Page 228: ...DTCTL register is set see page 1034 Tamper event see Hibernation Module on page 531 for more information Any of the following BOR trigger events VDDA under BOR setting VDD under BOR setting Software m...

Page 229: ...Control The TM4C1294NCPDT microcontroller provides an integrated LDO regulator that is used to provide power to the majority of the microcontroller s internal logic Figure 5 4 shows the power architec...

Page 230: ...clock source is connected to the OSC0 input pin or an external crystal is connected across the OSC0 input and OSC1 output pins If the PLL is being used the crystal value can be any frequency between...

Page 231: ...the system clock in run and sleep mode The Deep Sleep Clock Configuration register DSCLKCFG specifies the behavior of the clock system while in deep sleep mode These registers control the following c...

Page 232: ...urces in Figure 5 5 include a superset of peripherals available in the family Some peripheral clock sources may not be present on your specific device June 18 2014 232 Texas Instruments Production Dat...

Page 233: ...S 0 1 piosc GPIO PM4 LCD mosc ADC0 USB EMAC EPHY ADCCLK CS CLKDIV CS CLKDIV 2N PWMCLK PWMDIV USEPWMDIV PWM0 CLKDIV ADC1 DIVSCLK mosc piosc N RTCCLK DIVSCLK MII RMII CLK LFIOSC ALTCLKCFG SYSCLK lpc PTP...

Page 234: ...or without using the PLL and the system clock must be at least 30 MHz In addition only integer divisors should be used to achieve the 60 MHz USB clock source Fractional divisors may increase jitter a...

Page 235: ...teristics of a GPIO as listed in Electrical Characteristics on page 1818 System Clock Frequency The system clock SysClk is the clock that is distributed to the processor and the integrated peripherals...

Page 236: ...the trimmed value returned in the CT field 5 2 5 4 Main Oscillator MOSC The main oscillator supports the use of crystals from 5 to 25 MHz The system control s RSCLKCFG register can be configured to s...

Page 237: ...ence clocks for the PLL are the PIOSC and the MOSC The PLL is controlled by two registers PLLFREQ0 and PLLFREQ1 The PLL VCO frequency fVCO is determined through the following calculation fVCO fIN MDIV...

Page 238: ...320 5 0x4 0x40 64 25 480 5 0x0 0x60 96 5 480 6 0x0 0x50 80 6 480 8 0x0 0x3C 60 8 480 10 0x0 0x30 48 10 480 12 0x0 0x28 40 12 480 16 0x0 0x1E 30 16 480 6 0x2 0x50 80 18 480 20 0x0 0x18 24 20 480 24 0x0...

Page 239: ...ured to be clock gated during Run Sleep or Deep Sleep mode then software should ensure that there are no pending transfers or register accesses before or immediately after entering the clock gated mod...

Page 240: ...al with an invalid clock A software delay loop can be used at the beginning of the interrupt routine that is used to wake up a system from a WFI Wait For Interrupt instruction This stalls the executio...

Page 241: ...utilized as the clock source when entering Deep Sleep and the device enters and exits the Deep Sleep state normally The MOSC is not used as the clock source in Deep Sleep If the PIOSC has been configu...

Page 242: ...Flash memory and SRAM into different levels of power savings while in Sleep or Deep Sleep modes In addition software has the ability to control the LDO settings to gain a power advantage when running...

Page 243: ...registers have no effect since they are not on their own power domain Peripheral Memory Power Control When Deep Sleep is entered users have the capability to reduce power further in peripheral modules...

Page 244: ...ested values for the LDO in the various modes If software requests an LDO value that is too low or too high the value is not accepted and an error is reported in the SDPMST register Note When using th...

Page 245: ...the reset 5 2 6 6 Hardware System Service Request The Hardware System Service Request HSSR register is used to issue a request that returns a device to factory settings An HSSR consists of writing the...

Page 246: ...OSC is acting as the system clock 2 Power up the MOSC by clearing the NOXTAL bit in the MOSCCTL register 3 If single ended MOSC mode is required the MOSC is ready to use If crystal mode is required cl...

Page 247: ...e timing parameters to memory are within range through the following steps 1 If the change in system clock frequency changes the operational range of the timing parameters the MEMTIM0 register must be...

Page 248: ...scillator Statistics 0x0040 0040 RO PIOSCSTAT 0x154 292 PLL Frequency 0 0x0000 0000 RW PLLFREQ0 0x160 293 PLL Frequency 1 0x0000 0000 RW PLLFREQ1 0x164 294 PLL Status 0x0000 0000 RO PLLSTAT 0x168 295...

Page 249: ...nt 0x0000 0001 RO PPUSB 0x328 336 Ethernet PHY Peripheral Present 0x0000 0001 RO PPEPHY 0x330 337 Controller Area Network Peripheral Present 0x0000 0003 RO PPCAN 0x334 338 Analog to Digital Converter...

Page 250: ...000 0000 RW SRCAN 0x534 372 Analog to Digital Converter Software Reset 0x0000 0000 RW SRADC 0x538 373 Analog Comparator Software Reset 0x0000 0000 RW SRACMP 0x53C 374 Pulse Width Modulator Software Re...

Page 251: ...rpose Timer Sleep Mode Clock Gating Control 0x0000 0000 RW SCGCTIMER 0x704 406 General Purpose Input Output Sleep Mode Clock Gating Control 0x0000 0000 RW SCGCGPIO 0x708 409 Micro Direct Memory Access...

Page 252: ...hronous Serial Interface Deep Sleep Mode Clock Gating Control 0x0000 0000 RW DCGCSSI 0x81C 439 Inter Integrated Circuit Deep Sleep Mode Clock Gating Control 0x0000 0000 RW DCGCI2C 0x820 441 Universal...

Page 253: ...PCQEI 0x944 490 EEPROM Power Control 0x0000 0001 RW PCEEPROM 0x958 492 CRC Module Power Control 0x0000 0001 RW PCCCM 0x974 494 Ethernet MAC Power Control 0x0000 0001 RW PCEMAC 0x99C 496 Watchdog Timer...

Page 254: ...EEPROM 0xA58 520 CRC Module Peripheral Ready 0x0000 0000 RO PRCCM 0xA74 521 Ethernet MAC Peripheral Ready 0x0000 0000 RO PREMAC 0xA9C 522 Unique ID 0 RO UNIQUEID0 0xF20 522 Unique ID 1 RO UNIQUEID1 0x...

Page 255: ...ducts the value of a reserved bit should be preserved across a read modify write operation 0 RO reserved 31 DID0 Version This field defines the DID0 register format version The version number is numer...

Page 256: ...evision B first base layer revision 0x1 Revision C second base layer revision 0x2 and so on RO MAJOR 15 8 Minor Revision This field specifies the minor revision number of the microcontroller The minor...

Page 257: ...t Field DID1 Version This field defines the DID1 register format version The version number is numeric The value of the VER field is encoded as follows all other encodings are reserved Description Val...

Page 258: ...of the device The value is encoded as follows all other encodings are reserved Description Value Commercial temperature range 0x0 Industrial temperature range 0x1 Extended temperature range 0x2 0x3 R...

Page 259: ...RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VDD_UBOR reserved VDDA_UBOR reserved RW RW RO RO RO RO RO RO RW RW RO RO RO R...

Page 260: ...D trips under the VDD_BOR threshold found in Table 27 13 on page 1826 This field determines the action to take on the event Description Value No Action 0x0 System control interrupt 0x1 NMI 0x2 Reset 0...

Page 261: ...ss a read modify write operation 0x0000 00 RO reserved 31 9 MOSC Power Up Raw Interrupt Status Description Value Sufficient time has not passed for the MOSC to reach the expected frequency 0 Sufficien...

Page 262: ...ead modify write operation 0 RO reserved 2 Brown Out Reset Raw Interrupt Status Description Value A brown out condition is not currently active 0 A brown out condition is currently active 1 The approp...

Page 263: ...f a reserved bit should be preserved across a read modify write operation 0x0000 00 RO reserved 31 9 MOSC Power Up Interrupt Mask Description Value The MOSCPUPRIS interrupt is suppressed and not sent...

Page 264: ...f a reserved bit should be preserved across a read modify write operation 0 RO reserved 2 Brown Out Reset Interrupt Mask Description Value The BORRIS interrupt is suppressed and not sent to the interr...

Page 265: ...oss a read modify write operation 0x0000 00 RO reserved 31 9 MOSC Power Up Masked Interrupt Status Description Value When read a 0 indicates that sufficient time has not passed for the MOSC PLL to loc...

Page 266: ...ware should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 RO reserved 2 B...

Page 267: ...W RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 EXT POR BOR WDT0 SW WDT1 reserved HSSR reserved RW RW RW RW RW RW RO RO RO...

Page 268: ...enerated a reset since the previous power on reset Writing a 0 to this bit clears it 0 When read this bit indicates that Watchdog Timer 1 timed out and generated a reset 1 0 RW WDT1 5 Software Reset D...

Page 269: ...wn out reset has caused a reset event 1 0 RW BOR 2 Power On Reset Description Value When read this bit indicates that a power on reset has not generated a reset Writing a 0 to this bit clears it 0 Whe...

Page 270: ...1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VDD_UBOR reserved VDDA_UBOR reserved RW1C RO RO RO RW1C RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit...

Page 271: ...AIL reserved RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 EXTERNAL reserved POWER WDT0 reserved WDT1 reserved TAMPER...

Page 272: ...lity with future products the value of a reserved bit should be preserved across a read modify write operation 0 RO reserved 4 Watch Dog Timer WDT 0 NMI Description Value No WDT 0 timeout has occurred...

Page 273: ...RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CVAL MOSCIM NOXTAL PWRDN OSCRNG reserved RW RW RW RW RW RO RO RO RO RO RO...

Page 274: ...is bit and set the PWRDN bit in a single write access This bit should be set when a crystal or external oscillator is not connected to the OSC0 and OSC1 inputs to reduce power consumption 1 1 RW NOXTA...

Page 275: ...of the values in the PLLFREQ0 and PLLFREQ1 registers as applied to the PLL Until NEWFREQ is written to a 1 writes to the PLLFREQ0 and PLLFREQ1 are deferred When written with a 1 the values stored in...

Page 276: ...ce that becomes the oscillator clock OSCCLK source which is used when the PLL is bypassed during run or sleep modes Description Value PIOSC is oscillator source 0x0 reserved 0x1 LFIOSC is oscillator s...

Page 277: ...ns CPU Frequency range f in MHz 0x0 1 0x0 62 5 16 0x1 0 0x2 62 5 t 25 16 f 40 0x2 0 0x3 25 t 16 67 40 f 60 0x3 0 0x4 16 67 t 12 5 60 f 80 0x4 0 0x5 12 5 t 10 80 f 100 0x5 0 0x6 10 t 8 33 100 f 120 No...

Page 278: ...ith system clock falling 1 1 RW EBCE 21 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a r...

Page 279: ...scription Value Flash clock rising aligns with system clock rising 0 Flash clock rising aligns with system clock falling 1 1 RW FBCE 5 Software should not rely on the value of a reserved bit To provid...

Page 280: ...t Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a r...

Page 281: ...ource in the RSCLKCFG register prior to entering Deep Sleep If the PIOSC LFIOSC or Hibernation RTC Module Oscillator HIBLFIOSC or 32 kHz crystal is configured as the Run and Sleep clock source in the...

Page 282: ...bit should only be set after software configures the MOSCCTL register Setting the MOSCDPD bit masks writes to PWRDN bit in the MOSCCTL register 0 RW MOSCDPD 30 Software should not rely on the value of...

Page 283: ...eep Sleep clock divide by 1 or divide by 2 is desired the OSYSDIV bit field of the RSCLKCFG register must be configured for the desired Deep Sleep divider before entering Deep Sleep In this case the Q...

Page 284: ...0 0 0 0 0 Reset Description Reset Type Name Bit Field DIVSCLK Enable This bit enables the generation of the DIVSCLK clock output It resets to 0 to disable the output thereby reducing initial current p...

Page 285: ...clock to the output clock The output clock frequency is equal to the source clock frequency divided by the DIV field value plus 1 Description Value Divided by 1 0x0 Divided by 2 0x1 Divided by N N 0 R...

Page 286: ...Value The LDOSM bit of the DSLPPWRCFG register is ignored 0 The LDOSM bit of the DSLPPWRCFG register can be set to place the LDO in a low power mode when the deep sleep state is entered 1 0x1 RO LDOSM...

Page 287: ...ue of a reserved bit should be preserved across a read modify write operation 0 RO reserved 9 Flash Memory Sleep Deep Sleep Low Power Mode Present This bit determines whether the FLASHPM field in the...

Page 288: ...ture products the value of a reserved bit should be preserved across a read modify write operation 0 RO reserved 4 1 FPU Present This bit indicates if the FPU is present in the Cortex M4 core Descript...

Page 289: ...d for any update trim operation 1 0 RW UTEN 31 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved acr...

Page 290: ...Description Reset Type Name Bit Field User Trim Value User trim value that can be loaded into the PIOSC 0x0 RW UT 6 0 June 18 2014 290 Texas Instruments Production Data System Control...

Page 291: ...oss a read modify write operation 0x00 RO reserved 31 23 Default Trim Value This field contains the default trim value This value is loaded into the PIOSC after every full power up 0x40 RO DT 22 16 So...

Page 292: ...WR reserved RW RW RW RW RO RO RO RW RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MINT MFRAC RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW...

Page 293: ...RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 N reserved Q reserved RW RW RW RW RW RO RO RO RW RW RW RW RW RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 294: ...2 13 14 15 LOCK reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a res...

Page 295: ...ovide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x0000 00 RO reserved 31 6 Flash Power Modes Description Value Active Mode...

Page 296: ...mode provides the fastest time to sleep and wakeup but the highest power consumption while the microcontroller is in Sleep mode 0x0 Standby Mode SRAM is placed in standby mode while in Sleep mode 0x1...

Page 297: ...d bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x0000 00 RO reserved 31 10 LDO Sleep Mode Description Value LD...

Page 298: ...ftware should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x0 RO reserved...

Page 299: ...5 6 7 8 9 10 11 12 13 14 15 FWB reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on th...

Page 300: ...RO RO RO RO RO RW Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VLDO reserved RW RW RW RW RW RW RW RW RO RO RO RO RO RO RO RO Type 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 R...

Page 301: ...ld is only used for the LDO voltage when the VADJEN bit is set Description Value 0 90 V 0x12 0 95 V 0x13 1 00 V 0x14 1 05 V 0x15 1 10 V 0x16 1 15 V 0x17 1 20 V 0x18 reserved 0x19 0xFF Note When using...

Page 302: ...1 1 0 0 0 0 0 0 1 1 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit...

Page 303: ...RO RW Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VLDO reserved RW RW RW RW RW RW RW RW RO RO RO RO RO RO RO RO Type 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 Reset Descript...

Page 304: ...oltage in Deep Sleep mode The value of the field is only used for the LDO voltage when the VADJEN bit is set Description Value 0 90 V 0x12 0 95 V 0x13 1 00 V 0x14 1 05 V 0x15 1 10 V 0x16 1 15 V 0x17 1...

Page 305: ...1 0 0 1 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be p...

Page 306: ...4 5 6 7 8 9 10 11 12 13 14 15 SPDERR FPDERR PPDERR LDMINERR LSMINERR reserved LMAXERR PPDW reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Descripti...

Page 307: ...C was in use by a peripheral 1 0 RO PPDW 7 VLDO Value Above Maximum Error Description Value No error 0 An error has occurred because software has requested that the LDO voltage be above the maximum va...

Page 308: ...Deep Sleep and it is not possible to power down the PIOSC In this situation the PIOSC is not powered down when entering Deep Sleep mode 1 0 RO PPDERR 2 Flash Memory Power Down Request Error Descripti...

Page 309: ...RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 EXTRES BOR WDOG0 WDOG1 reserved RW RW RW RW RW RW RW RW RO RO RO RO RO RO...

Page 310: ...erved Default operation is performed 0x0 0x1 Brown Out Reset issues system reset 0x2 Brown Out Reset issues a simulated POR sequence default 0x3 0x3 RW BOR 3 2 External RST Pin Operation Description V...

Page 311: ...W R0 W R0 W Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CDOFF RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Descriptio...

Page 312: ...TAT reserved reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserv...

Page 313: ...RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PWRCTL reserved RW RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 1 0 0 0 0 0 0...

Page 314: ...RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PWRSTAT MEMSTAT reserved reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0...

Page 315: ...1 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PWRCTL reserved RW RW RO RO RO...

Page 316: ...eset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PWRSTAT MEMSTAT reserved reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit...

Page 317: ...21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PWRCTL reserved RW RW RO RO R...

Page 318: ...eset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PWRSTAT MEMSTAT reserved reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit...

Page 319: ...23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PWRCTL reserved RW RW RO RO RO RO R...

Page 320: ...t 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 P0 P1 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should...

Page 321: ...ue of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 RO reserved 31 8 16 32 Bit General Purpose Tim...

Page 322: ...2 is not present 0 16 32 bit general purpose timer module 2 is present 1 0x1 RO P2 2 16 32 Bit General Purpose Timer 1 Present Description Value 16 32 bit general purpose timer module 1 is not presen...

Page 323: ...RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide comp...

Page 324: ...IO Port J is present 1 0x1 RO P8 8 GPIO Port H Present Description Value GPIO Port H is not present 0 GPIO Port H is present 1 0x1 RO P7 7 GPIO Port G Present Description Value GPIO Port G is not pres...

Page 325: ...ion Value GPIO Port C is not present 0 GPIO Port C is present 1 0x1 RO P2 2 GPIO Port B Present Description Value GPIO Port B is not present 0 GPIO Port B is present 1 0x1 RO P1 1 GPIO Port A Present...

Page 326: ...RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 P0 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 0 0 0 0 0 0 0...

Page 327: ...RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 P0 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Descriptio...

Page 328: ...O RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 P0 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Re...

Page 329: ...O RO RO RO RO RO RO RO RO RO RO Type 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with f...

Page 330: ...scription Value UART module 2 is not present 0 UART module 2 is present 1 0x1 RO P2 2 UART Module 1 Present Description Value UART module 1 is not present 0 UART module 1 is present 1 0x1 RO P1 1 UART...

Page 331: ...RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 P0 P1 P2 P3 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type...

Page 332: ...iption Reset Type Name Bit Field SSI Module 0 Present Description Value SSI module 0 is not present 0 SSI module 0 is present 1 0x1 RO P0 0 June 18 2014 332 Texas Instruments Production Data System Co...

Page 333: ...O RO RO RO RO Type 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the...

Page 334: ...scription Value I2 C module 3 is not present 0 I2 C module 3 is present 1 0x1 RO P3 3 I2 C Module 2 Present Description Value I2 C module 2 is not present 0 I2 C module 2 is present 1 0x1 RO P2 2 I2 C...

Page 335: ...O RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 P0 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 336: ...RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 P0 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 337: ...0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 P0 P1 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Softwa...

Page 338: ...0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 P0 P1 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bi...

Page 339: ...23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 P0 reserved RO RO RO RO RO RO RO R...

Page 340: ...O RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 P0 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 0 0 0 0 0 0 0 0 0 0...

Page 341: ...O RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 P0 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 0 0 0 0 0 0 0 0 0 0 0 0...

Page 342: ...0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 P0 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Fi...

Page 343: ...0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 P0 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name B...

Page 344: ...0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 P0 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software...

Page 345: ...1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 P0 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rel...

Page 346: ...0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 P0 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software sh...

Page 347: ...RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 P0 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0...

Page 348: ...RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 P0 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Desc...

Page 349: ...O RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 P0 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Descript...

Page 350: ...RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 P0 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R...

Page 351: ...O RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 P0 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description...

Page 352: ...RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 P0 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0...

Page 353: ...RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 P0 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0...

Page 354: ...SRWD Base 0x400F E000 Offset 0x500 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 355: ...0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 R1 R2...

Page 356: ...module 3 is not reset 0 16 32 bit general purpose timer module 3 is reset 1 0 RW R3 3 16 32 Bit General Purpose Timer 2 Software Reset Description Value 16 32 bit general purpose timer module 2 is not...

Page 357: ...Base 0x400F E000 Offset 0x508 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R...

Page 358: ...0 GPIO Port L is reset 1 0 RW R10 10 GPIO Port K Software Reset Description Value GPIO Port K is not reset 0 GPIO Port K is reset 1 0 RW R9 9 GPIO Port J Software Reset Description Value GPIO Port J i...

Page 359: ...scription Value GPIO Port D is not reset 0 GPIO Port D is reset 1 0 RW R3 3 GPIO Port C Software Reset Description Value GPIO Port C is not reset 0 GPIO Port C is reset 1 0 RW R2 2 GPIO Port B Softwar...

Page 360: ...d be used to reset the DMA module Micro Direct Memory Access Software Reset SRDMA Base 0x400F E000 Offset 0x50C Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO...

Page 361: ...to reset the EPI module EPI Software Reset SREPI Base 0x400F E000 Offset 0x510 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO...

Page 362: ...d to reset the Hibernation module Hibernation Software Reset SRHIB Base 0x400F E000 Offset 0x514 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO...

Page 363: ...er Software Reset SRUART Base 0x400F E000 Offset 0x518 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0...

Page 364: ...set Description Value UART module 3 is not reset 0 UART module 3 is reset 1 0 RW R3 3 UART Module 2 Software Reset Description Value UART module 2 is not reset 0 UART module 2 is reset 1 0 RW R2 2 UAR...

Page 365: ...e Reset SRSSI Base 0x400F E000 Offset 0x51C Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0...

Page 366: ...Reset Description Value SSI module 1 is not reset 0 SSI module 1 is reset 1 0 RW R1 1 SSI Module 0 Software Reset Description Value SSI module 0 is not reset 0 SSI module 0 is reset 1 0 RW R0 0 June 1...

Page 367: ...6 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 R1 R2 R3 R4...

Page 368: ...module 4 is reset 1 0 RW R4 4 I2 C Module 3 Software Reset Description Value I2 C module 3 is not reset 0 I2 C module 3 is reset 1 0 RW R3 3 I2 C Module 2 Software Reset Description Value I2 C module...

Page 369: ...to reset the USB module Universal Serial Bus Software Reset SRUSB Base 0x400F E000 Offset 0x528 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO...

Page 370: ...eset the Ethernet PHY module Ethernet PHY Software Reset SREPHY Base 0x400F E000 Offset 0x530 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO...

Page 371: ...Reset SRCAN Base 0x400F E000 Offset 0x534 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0...

Page 372: ...rter Software Reset SRADC Base 0x400F E000 Offset 0x538 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0...

Page 373: ...g comparator module Analog Comparator Software Reset SRACMP Base 0x400F E000 Offset 0x53C Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO...

Page 374: ...e used to reset the PWM modules Pulse Width Modulator Software Reset SRPWM Base 0x400F E000 Offset 0x540 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO...

Page 375: ...reset the QEI modules Quadrature Encoder Interface Software Reset SRQEI Base 0x400F E000 Offset 0x544 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO...

Page 376: ...accessed EEPROM Software Reset SREEPROM Base 0x400F E000 Offset 0x558 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO...

Page 377: ...module CRC Module Software Reset SRCCM Base 0x400F E000 Offset 0x574 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO...

Page 378: ...controller MAC module Ethernet MAC Software Reset SREMAC Base 0x400F E000 Offset 0x59C Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO...

Page 379: ...RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 R1 reserved RW RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Desc...

Page 380: ...O RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products...

Page 381: ...de Clock Gating Control Description Value 16 32 bit general purpose timer module 2 is disabled 0 Enable and provide a clock to 16 32 bit general purpose timer module 2 in Run mode 1 0 RW R2 2 16 32 Bi...

Page 382: ...4 reserved RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To p...

Page 383: ...GPIO Port H Run Mode Clock Gating Control Description Value GPIO Port H is disabled 0 Enable and provide a clock to GPIO Port H in Run mode 1 0 RW R7 7 GPIO Port G Run Mode Clock Gating Control Descr...

Page 384: ...ort C is disabled 0 Enable and provide a clock to GPIO Port C in Run mode 1 0 RW R2 2 GPIO Port B Run Mode Clock Gating Control Description Value GPIO Port B is disabled 0 Enable and provide a clock t...

Page 385: ...000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 re...

Page 386: ...7 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 reserved RW RO...

Page 387: ...9 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 reserved RW RO RO RO...

Page 388: ...served RW RW RW RW RW RW RW RW RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provi...

Page 389: ...abled 0 Enable and provide a clock to UART module 2 in Run mode 1 0 RW R2 2 UART Module 1 Run Mode Clock Gating Control Description Value UART module 1 is disabled 0 Enable and provide a clock to UART...

Page 390: ...W RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility...

Page 391: ...10 11 12 13 14 15 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 reserved RW RW RW RW RW RW RW RW RW RW RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software shou...

Page 392: ...W R4 4 I2 C Module 3 Run Mode Clock Gating Control Description Value I2 C module 3 is disabled 0 Enable and provide a clock to I2 C module 3 in Run mode 1 0 RW R3 3 I2 C Module 2 Run Mode Clock Gating...

Page 393: ...00 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 reserved...

Page 394: ...0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 reserved...

Page 395: ...RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 R1 reserved RW RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0...

Page 396: ...RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 R1 reserved RW RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0...

Page 397: ...18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 reserved RW RO RO...

Page 398: ...0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R...

Page 399: ...0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 r...

Page 400: ...30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 reserved RW RO RO RO RO RO RO RO RO RO RO RO RO RO R...

Page 401: ...19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 reserved RW RO RO RO...

Page 402: ...000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 reserve...

Page 403: ...6 7 8 9 10 11 12 13 14 15 S0 S1 reserved RW RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on th...

Page 404: ...eset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify writ...

Page 405: ...k Gating Control Description Value 16 32 bit general purpose timer module 2 is disabled in sleep mode 0 Enable and provide a clock to 16 32 bit general purpose timer module 2 in sleep mode 1 0 RW S2 2...

Page 406: ...0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be pr...

Page 407: ...t H Sleep Mode Clock Gating Control Description Value GPIO Port H is disabled in sleep mode 0 Enable and provide a clock to GPIO Port H in sleep mode 1 0 RW S7 7 GPIO Port G Sleep Mode Clock Gating Co...

Page 408: ...d in sleep mode 0 Enable and provide a clock to GPIO Port C in sleep mode 1 0 RW S2 2 GPIO Port B Sleep Mode Clock Gating Control Description Value GPIO Port B is disabled in sleep mode 0 Enable and p...

Page 409: ...reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 S0 reserved RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO T...

Page 410: ...RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 S0 reserved RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0...

Page 411: ...RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 S0 reserved RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 0 0 0 0 0 0 0...

Page 412: ...0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be...

Page 413: ...sleep mode 0 Enable and provide a clock to UART module 2 in sleep mode 1 0 RW S2 2 UART Module 1 Sleep Mode Clock Gating Control Description Value UART module 1 is disabled in sleep mode 0 Enable and...

Page 414: ...escription Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read...

Page 415: ...Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify wri...

Page 416: ...sabled in sleep mode 0 Enable and provide a clock to I2 C module 3 in sleep mode 1 0 RW S3 3 I2 C Module 2 Sleep Mode Clock Gating Control Description Value I2 C module 2 is disabled in sleep mode 0 E...

Page 417: ...ved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 S0 reserved RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0...

Page 418: ...served RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 S0 reserved RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type...

Page 419: ...0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 S0 S1 reserved RW RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field S...

Page 420: ...0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 S0 S1 reserved RW RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit...

Page 421: ...RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 S0 reserved RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0...

Page 422: ...30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 S0 reserved RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO...

Page 423: ...31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 S0 reserved RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO...

Page 424: ...O RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 S0 reserved RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset De...

Page 425: ...O RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 S0 reserved RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0...

Page 426: ...d RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 S0 reserved RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0...

Page 427: ...10 11 12 13 14 15 D0 D1 reserved RW RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value...

Page 428: ...Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 R...

Page 429: ...Gating Control Description Value 16 32 bit general purpose timer module 2 is disabled in deep sleep mode 0 Enable and provide a clock to 16 32 bit general purpose timer module 2 in deep sleep mode 1 0...

Page 430: ...cription Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read m...

Page 431: ...p Sleep Mode Clock Gating Control Description Value GPIO Port H is disabled in deep sleep mode 0 Enable and provide a clock to GPIO Port H in deep sleep mode 1 0 RW D7 7 GPIO Port G Deep Sleep Mode Cl...

Page 432: ...sleep mode 0 Enable and provide a clock to GPIO Port C in deep sleep mode 1 0 RW D2 2 GPIO Port B Deep Sleep Mode Clock Gating Control Description Value GPIO Port B is disabled in deep sleep mode 0 En...

Page 433: ...reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 D0 reserved RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO T...

Page 434: ...RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 D0 reserved RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0...

Page 435: ...RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 D0 reserved RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 0 0 0 0 0 0 0...

Page 436: ...RW RW RW RW RW RW RW RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compat...

Page 437: ...Sleep Mode Clock Gating Control Description Value UART module 2 is disabled in deep sleep mode 0 Enable and provide a clock to UART module 2 in deep sleep mode 1 0 RW D2 2 UART Module 1 Deep Sleep Mod...

Page 438: ...ame Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation...

Page 439: ...eld Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 RO rese...

Page 440: ...eep mode 0 Enable and provide a clock to I2 C module 3 in deep sleep mode 1 0 RW D3 3 I2 C Module 2 Deep Sleep Mode Clock Gating Control Description Value I2 C module 2 is disabled in deep sleep mode...

Page 441: ...ved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 D0 reserved RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0...

Page 442: ...served RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 D0 reserved RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type...

Page 443: ...t 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 D0 D1 reserved RW RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should...

Page 444: ...0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 D0 D1 reserved RW RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field So...

Page 445: ...RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 D0 reserved RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0...

Page 446: ...30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 D0 reserved RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO...

Page 447: ...31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 D0 reserved RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO...

Page 448: ...RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 D0 reserved RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Descripti...

Page 449: ...O RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 D0 reserved RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0...

Page 450: ...d RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 D0 reserved RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0...

Page 451: ...Sn or Dn Value in Respective RCGCx SCGCx or DCGCx Register Module is not powered and does not receive a clock In this case the peripheral s state is not retained This is the lowest power consumption s...

Page 452: ...powered but does not receive a clock In this case the module is inactive 1 1 RW P1 1 Watchdog Timer 0 Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCWD SCGC...

Page 453: ...ed but does not receive a clock The table below details the differences Table 5 17 Module Power Control Description Pn Rn Sn or Dn Value in Respective RCGCx SCGCx or DCGCx Register Module is not power...

Page 454: ...tate is not retained This configuration provides the lowest power consumption state 0 Timer 6 module is powered but does not receive a clock In this case the module is inactive 1 1 RW P6 6 General Pur...

Page 455: ...ut does not receive a clock In this case the module is inactive 1 1 RW P2 2 General Purpose Timer 1 Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCTIMER SCGC...

Page 456: ...s not receive a clock The table below details the differences Table 5 18 Module Power Control Description Pn Rn Sn or Dn Value in Respective RCGCx SCGCx or DCGCx Register Module is not powered and doe...

Page 457: ...not retained This configuration provides the lowest power consumption state 0 GPIO Port P is powered but does not receive a clock In this case the module is inactive 1 1 RW P13 13 GPIO Port N Power Co...

Page 458: ...s powered but does not receive a clock In this case the module is inactive 1 1 RW P9 9 GPIO Port J Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCGPIO SCGCGP...

Page 459: ...ut does not receive a clock In this case the module is inactive 1 1 RW P5 5 GPIO Port E Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCGPIO SCGCGPIO or DCGCG...

Page 460: ...gister is clear Description Value GPIO Port B is not powered and does not receive a clock In this case the module s state is not retained This configuration provides the lowest power consumption state...

Page 461: ...but does not receive a clock The table below details the differences Table 5 19 Module Power Control Description Pn Rn Sn or Dn Value in Respective RCGCx SCGCx or DCGCx Register Module is not powered...

Page 462: ...Pn bit encodings are not applicable if the corresponding bit in the RCGCDMA SCGCDMA or DCGCDMA register is clear Description Value The DMA module is not powered and does not receive a clock In this c...

Page 463: ...but does not receive a clock The table below details the differences Table 5 20 Module Power Control Description Pn Rn Sn or Dn Value in Respective RCGCx SCGCx or DCGCx Register Module is not powered...

Page 464: ...Pn bit encodings are not applicable if the corresponding bit in the RCGCEPI SCGCEPI or DCGCEPI register is clear Description Value The EPI module is not powered and does not receive a clock In this c...

Page 465: ...Sn or Dn Value in Respective RCGCx SCGCx or DCGCx Register Module is not powered and does not receive a clock In this case the peripheral s state is not retained This is the lowest power consumption...

Page 466: ...ister is clear Description Value The HIB module is not powered and does not receive a clock In this case the module s state is not retained This configuration provides the lowest power consumption sta...

Page 467: ...does not receive a clock The table below details the differences Table 5 22 Module Power Control Description Pn Rn Sn or Dn Value in Respective RCGCx SCGCx or DCGCx Register Module is not powered and...

Page 468: ...e is not retained This configuration provides the lowest power consumption state 0 The UART module 6 is powered but does not receive a clock In this case the module is inactive 1 1 RW P6 6 UART Module...

Page 469: ...ut does not receive a clock In this case the module is inactive 1 1 RW P2 2 UART Module 1 Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCUART SCGCUART or DCG...

Page 470: ...ered but does not receive a clock The table below details the differences Table 5 23 Module Power Control Description Pn Rn Sn or Dn Value in Respective RCGCx SCGCx or DCGCx Register Module is not pow...

Page 471: ...retained This configuration provides the lowest power consumption state 0 The SSI module 2 is powered but does not receive a clock In this case the module is inactive 1 1 RW P2 2 SSI Module 1 Power Co...

Page 472: ...n Value in Respective RCGCx SCGCx or DCGCx Register Module is not powered and does not receive a clock In this case the peripheral s state is not retained This is the lowest power consumption state of...

Page 473: ...ut does not receive a clock In this case the module is inactive 1 1 RW P8 8 I2 C Module 7 Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCI2C SCGCI2C or DCGCI...

Page 474: ...powered but does not receive a clock In this case the module is inactive 1 1 RW P4 4 I2 C Module 3 Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCI2C SCGCI2...

Page 475: ...ut does not receive a clock In this case the module is inactive 1 1 RW P1 1 I2 C Module 0 Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCI2C SCGCI2C or DCGCI...

Page 476: ...ock In this case the peripheral s state is not retained This is the lowest power consumption state of any peripheral since it consumes no dynamic nor leakage current Hardware should perform a peripher...

Page 477: ...Description Value The USB module is not powered and does not receive a clock In this case the module s state is not retained This configuration provides the lowest power consumption state 0 The USB m...

Page 478: ...a peripheral reset if the active mode changes and the RCGCx SCGCx or DCGCx register is a 1 or the P0 bit is changed to a 1 Software must re initialize the peripheral when re enabled due to the loss of...

Page 479: ...encodings are not applicable if the corresponding bit in the RCGCEPHY SCGCEPHY or DCGCEPHY register is clear Description Value The EPHY module is not powered and does not receive a clock In this case...

Page 480: ...k In this case the peripheral s state is not retained This is the lowest power consumption state of any peripheral since it consumes no dynamic nor leakage current Hardware should perform a peripheral...

Page 481: ...ut does not receive a clock In this case the module is inactive 1 1 RW P1 1 CAN Module 0 Power Control The Pn bit encodings are not applicable if the corresponding bit in the RCGCCAN SCGCCAN or DCGCCA...

Page 482: ...powered but does not receive a clock The table below details the differences Table 5 28 Module Power Control Description Pn Rn Sn or Dn Value in Respective RCGCx SCGCx or DCGCx Register Module is not...

Page 483: ...retained This configuration provides the lowest power consumption state 0 The ADC module 1 is powered but does not receive a clock In this case the module is inactive 1 1 RW P1 1 ADC Module 0 Power Co...

Page 484: ...ription Pn Rn Sn or Dn Value in Respective RCGCx SCGCx or DCGCx Register Module is not powered and does not receive a clock In this case the peripheral s state is not retained This is the lowest power...

Page 485: ...ription Value The Analog Comparator module is not powered and does not receive a clock In this case the module s state is not retained This configuration provides the lowest power consumption state 0...

Page 486: ...Pn Rn Sn or Dn Value in Respective RCGCx SCGCx or DCGCx Register Module is not powered and does not receive a clock In this case the peripheral s state is not retained This is the lowest power consum...

Page 487: ...Description Value The PWM module 0 is not powered and does not receive a clock In this case the module s state is not retained This configuration provides the lowest power consumption state 0 The PWM...

Page 488: ...s powered but does not receive a clock The table below details the differences Table 5 31 Module Power Control Description Pn Rn Sn or Dn Value in Respective RCGCx SCGCx or DCGCx Register Module is no...

Page 489: ...encodings are not applicable if the corresponding bit in the RCGCQEI SCGCQEI or DCGCQEI register is clear Description Value QEI module 0 is not powered and does not receive a clock In this case the m...

Page 490: ...r Control Description Pn Rn Sn or Dn Value in Respective RCGCx SCGCx or DCGCx Register Module is not powered and does not receive a clock In this case the peripheral s state is not retained This is th...

Page 491: ...lear Description Value The EEPROM module is not powered and does not receive a clock In this case the module s state is not retained This configuration provides the lowest power consumption state 0 Th...

Page 492: ...ock In this case the peripheral s state is not retained This is the lowest power consumption state of any peripheral since it consumes no dynamic nor leakage current Hardware should perform a peripher...

Page 493: ...Description Value The CRC module is not powered and does not receive a clock In this case the module s state is not retained This configuration provides the lowest power consumption state 0 The CRC m...

Page 494: ...e a clock In this case the peripheral s state is not retained This is the lowest power consumption state of any peripheral since it consumes no dynamic nor leakage current Hardware should perform a pe...

Page 495: ...Description Value Ethernet MAC Module 0 is not powered and does not receive a clock In this case the module s state is not retained This configuration provides the lowest power consumption state 0 Et...

Page 496: ...RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 R1 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0...

Page 497: ...RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compati...

Page 498: ...eral Ready Description Value 16 32 bit timer module 2 is not ready for access It is unclocked unpowered or in the process of completing a reset sequence 0 16 32 bit timer module 2 is ready for access...

Page 499: ...12 13 14 15 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field...

Page 500: ...ripheral Ready Description Value GPIO Port J is not ready for access It is unclocked unpowered or in the process of completing a reset sequence 0 GPIO Port J is ready for access 1 0 RO R8 8 GPIO Port...

Page 501: ...dy Description Value GPIO Port C is not ready for access It is unclocked unpowered or in the process of completing a reset sequence 0 GPIO Port C is ready for access 1 0 RO R2 2 GPIO Port B Peripheral...

Page 502: ...A Base 0x400F E000 Offset 0xA0C Type RO reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 503: ...ype RO reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 1...

Page 504: ...et 0xA14 Type RO reset 0x0000 0001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8...

Page 505: ...2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 R1 R2 R3 R4 R5 R6 R7 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Sof...

Page 506: ...heral Ready Description Value UART module 2 is not ready for access It is unclocked unpowered or in the process of completing a reset sequence 0 UART module 2 is ready for access 1 0 RO R2 2 UART Modu...

Page 507: ...6 7 8 9 10 11 12 13 14 15 R0 R1 R2 R3 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rel...

Page 508: ...pheral Ready Description Value SSI module 0 is not ready for access It is unclocked unpowered or in the process of completing a reset sequence 0 SSI module 0 is ready for access 1 0 RO R0 0 June 18 20...

Page 509: ...13 14 15 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rel...

Page 510: ...rocess of completing a reset sequence 0 I2 C module 4 is ready for access 1 0 RO R4 4 I2 C Module 3 Peripheral Ready Description Value I2 C module 3 is not ready for access It is unclocked unpowered o...

Page 511: ...y Description Value I2 C module 0 is not ready for access It is unclocked unpowered or in the process of completing a reset sequence 0 I2 C module 0 is ready for access 1 0 RO R0 0 511 June 18 2014 Te...

Page 512: ...0x400F E000 Offset 0xA28 Type RO reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset...

Page 513: ...30 Type RO reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10...

Page 514: ...reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 R1 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO...

Page 515: ...ed RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R0 R1 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type...

Page 516: ...ffset 0xA3C Type RO reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6...

Page 517: ...E000 Offset 0xA40 Type RO reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3...

Page 518: ...PRQEI Base 0x400F E000 Offset 0xA44 Type RO reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 519: ...et 0xA58 Type RO reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8...

Page 520: ...00 Offset 0xA74 Type RO reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4...

Page 521: ...C Type RO reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 1...

Page 522: ...be used to initiate secure boot processes or as a serial number for USB or other end applications Unique ID n UNIQUEIDn Base 0x400F E000 Offset 0xF20 Type RO reset 16 17 18 19 20 21 22 23 24 25 26 27...

Page 523: ...status is always visible via the System Exception Raw Interrupt Status SYSEXCRIS register Interrupts are always cleared for both the SYSEXCMIS and SYSEXCRIS registers by writing a 1 to the correspond...

Page 524: ...of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x0000 00 RO reserved 31 6 Floating Point Inexact...

Page 525: ...rrupt Status Description Value No interrupt 0 A floating point divide by 0 exception has occurred 1 This bit is cleared by writing a 1 to the DZCIC bit in the SYSEXCIC register 0 RO FPDZCRIS 1 Floatin...

Page 526: ...not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x0000 00 RW reserved 31 6 F...

Page 527: ...Value The FPDZCRIS interrupt is suppressed and not sent to the interrupt controller 0 An interrupt is sent to the interrupt controller when the FPDZCRIS bit in the SYSEXCRIS register is set 1 0 RW FP...

Page 528: ...value of a reserved bit should be preserved across a read modify write operation 0x0000 00 RO reserved 31 6 Floating Point Inexact Exception Masked Interrupt Status Description Value An interrupt has...

Page 529: ...alue An interrupt has not occurred or is masked 0 An unmasked interrupt was signaled due to a divide by 0 exception 1 This bit is cleared by writing a 1 to the FPDZCIC bit in the SYSEXCIC register 0 R...

Page 530: ...xception Interrupt Clear Writing a 1 to this bit clears the FPIXCRIS bit in the SYSEXCRIS register and the FPIXCMIS bit in the SYSEXCMIS register 0 W1C FPIXCIC 5 Floating Point Overflow Exception Inte...

Page 531: ...counter 32 bit RTC seconds match register and a 15 bit sub seconds match for timed wake up and interrupt generation with 1 32 768 second resolution RTC predivider trim for making fine adjustments to...

Page 532: ...neration with optional wake on low battery GPIO pin state can be retained during hibernation Clock source from an internal low frequency oscillator HIB LFIOSC or a 32 768 kHz external crystal or oscil...

Page 533: ...ription The following table lists the external signals of the Hibernation module and describes the function of each The RTCCLK and TMPR 3 0 signals are alternate functions for a GPIO signal and defaul...

Page 534: ...odule It is normally connected to the positive terminal of a battery and serves as the battery backup Hibernation module power source supply Power fixed 68 VBAT An external input that brings the proce...

Page 535: ...tion when the Hibernation modules registers can be accessed Alternatively software may make use of the WRC bit in the Hibernation Control HIBCTL register to ensure that the required timing gap has ela...

Page 536: ...oscillator HIB LFIOSC has a wide frequency variation therefore the RTC is not accurate when using this clock source It is not recommended to use the HIB LFIOSC as an RTC clock source The Hibernation m...

Page 537: ...ed from crystal vendor load capacitance specifications RPU Pull up resistor is 200 k RBAT 51 5 CBAT 0 1 F 20 See Hibernation Clock Source Specifications on page 1837 for specific parameter values Figu...

Page 538: ...ditional circuitry is required for system start up without a battery or with a depleted battery Using a regulator to provide both VDD and VBAT with a switch enabled by HIB to remove VDD during hiberna...

Page 539: ...In addition a software trim register is implemented to allow the user to compensate for oscillator inaccuracies using software 7 3 5 1 RTC Counter Seconds Subseconds Mode The clock signal to the RTC i...

Page 540: ...ng Hibernate mode the processor can be programmed to wake from Hibernate mode by setting the RTCWEN bit in the HIBCTL register The processor can also be programmed to generate an interrupt to the inte...

Page 541: ...divider trim register HIBRTCT This register has a nominal value of 0x7FFF and is used for one second out of every 64 seconds in RTC counter mode when bits 5 0 in the HIBRTCC register change from 0x00...

Page 542: ...r Behavior with a TRIM Value of 0x7FFC RTCCLK RTCC 6 0 RTCSSC 0x00 0x7FFD 0x7FFE 0x01 0x7FFF 0x7FFD 0x7FFE 0x7FFF 7 3 6 Tamper The Tamper module provides a user with mechanisms to detect respond to an...

Page 543: ...Figure 7 8 on page 543 This implies if two Tamper inputs are asserted and one deasserts the glitch filter runs to timeout or until the second Tamper input is deasserted The glitch filter or tamper log...

Page 544: ...he following status is logged The RTC seconds or calendar values of year minutes day of month hours and seconds in the HIBTPLOG0 2 4 6 registers Note 24 hour mode must be used if RTC calendar mode is...

Page 545: ...are powered from the battery or an auxiliary power supply and therefore retained during hibernation The processor software can save state information in this memory prior to hibernation and recover t...

Page 546: ...on page 1464 must be switched off 7 3 10 Initiating Hibernate Hibernate mode is initiated when the HIBREQ bit of the HIBCTL register is set If a wake up condition has not been configured using the PIN...

Page 547: ...onfiguration the battery voltage is checked every 512 seconds while in hibernation If the voltage is below the level specified by the VBATSEL field the LOWBAT interrupt is set in the HIBRIS register U...

Page 548: ...in the Hibernation Interrupt Mask HIBIM register Pending interrupts can be cleared by writing the corresponding bit in the Hibernation Interrupt Clear HIBIC register 7 4 Initialization and Configurat...

Page 549: ...nation module and clock are already powered by examining the CLK32EN bit of the HIBCTL register 7 4 2 RTC Match Functionality No Hibernation Use the following steps to implement the RTC match function...

Page 550: ...ister at offset 0x02C 4 When the IOWRC bit in the HIBIO register is read as 1 clear the WUUNLK bit in the HIBIO register to lock the current pad configuration so that any other writes to the WURSTEN b...

Page 551: ...has triggered Note Unlike other functions the Tamper pins do not need to be configured for the GPIO in the GPIOAFSEL register The Tamper IO Control and Status HIBTPIO register overrides configuration...

Page 552: ...and the PINWEN bits in the HIBCTL register are clear and the TPEN bit in the HIBTPCTL register is clear 2 A cold POR occurs when both the VDD and VBAT supplies are removed Any other reset condition i...

Page 553: ...0000 RW HIBTPCTL 0x400 589 HIB Tamper Status 0x0000 0000 RW1C HIBTPSTAT 0x404 591 HIB Tamper I O Control 0x0000 0000 RW HIBTPIO 0x410 595 HIB Tamper Log 0 0x0000 0000 RO HIBTPLOG0 0x4E0 596 HIB Tampe...

Page 554: ...the read is valid Note There is a minimum system clock rate of three times the HIB clock rate to properly read the HIBRTCC register Hibernation RTC Counter HIBRTCC Base 0x400F C000 Offset 0x000 Type R...

Page 555: ...OWK and WC of the HIBIC register do not require waiting for write to complete Because these registers are clocked by the system clock writes to these registers bits are immediate Writing to registers...

Page 556: ...ccess Timing on page 535 The HIBIO register and bits RSTWK PADIOWK and WC of the HIBIC register do not require waiting for write to complete Because these registers are clocked by the system clock wri...

Page 557: ...0 0 0 0 0 0 0 0 1 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RTCEN HIBREQ reserved RTCWEN PINWEN reserved CLK32EN VABORT VDD3ON BATWKEN BATCHK reserved VBATSEL reserved RW RW RO RW RW RO RW RW RW RW...

Page 558: ...ck source is enabled 0 HIB Low frequency oscillator HIB LFIOSC is enabled 1 Note The HIB low frequency oscillator has a wide frequency variation therefore the RTC is not accurate when using this clock...

Page 559: ...battery comparator cycle is not active Writing a 0 has no effect 0 When read indicates the low battery comparator cycle has not completed Setting this bit initiates a low battery comparator cycle If t...

Page 560: ...re entering hibernation If VBAT is less than the voltage specified by VBATSEL the microcontroller does not go into hibernation 1 0 RW VABORT 7 Clocking Enable This bit must be enabled to use the Hiber...

Page 561: ...Request Description Value No hibernation request 0 Set this bit to initiate hibernation 1 After a wake up event this bit is automatically cleared by hardware A hibernation request is ignored if both...

Page 562: ...400F C000 Offset 0x014 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1...

Page 563: ...sent to the interrupt controller when the EXTW bit in the HIBRIS register is set 1 0 RW EXTW 3 Low Battery Voltage Interrupt Mask Description Value The LOWBAT interrupt is suppressed and not sent to t...

Page 564: ...ed bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x0000 000 RO reserved 31 8 VDD Fail Raw Interrupt Status Desc...

Page 565: ...ription Value The battery voltage has not dropped below VLOWBAT 0 The battery voltage dropped below VLOWBAT 1 This bit is cleared by writing a 1 to the LOWBAT bit in the HIBIC register 0 RO LOWBAT 2 S...

Page 566: ...tion Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modif...

Page 567: ...nterrupt has not occurred or is masked 0 An unmasked interrupt was signaled due to a low battery voltage condition 1 This bit is cleared by writing a 1 to the LOWBAT bit in the HIBIC register 0 RO LOW...

Page 568: ...RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the val...

Page 569: ...reserved bit should be preserved across a read modify write operation 0 RO reserved 1 RTC Alert0 Masked Interrupt Clear Writing a 1 to this bit clears the RTCALT0 bit in the HIBRIS and HIBMIS register...

Page 570: ...TL and HIBIM before the CLK32EN bit in the HIBCTL register has been set may produce unexpected results Hibernation RTC Trim HIBRTCT Base 0x400F C000 Offset 0x024 Type RW reset 0x0000 7FFF 16 17 18 19...

Page 571: ...mes the HIB clock rate to properly read the HIBRTCSS register Hibernation RTC Sub Seconds HIBRTCSS Base 0x400F C000 Offset 0x028 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30...

Page 572: ...e Bit Field I O Write Complete Indicates whether or not the configuration that was programmed by the WURSTEN bit or GPIOWAKEPEN and GPIOWAKELVL registers have propagated through the pad ring Descripti...

Page 573: ...rs GPIOWAKEPEN and GPIOWAKELVL is ignored 0 Implement the I O WAKE configuration level and enables for the external RST pin and or GPIO wake enabled pins 1 Note This bit must be cleared before issuing...

Page 574: ...ccess Timing on page 535 The HIBIO register and bits RSTWK PADIOWK and WC of the HIBIC register do not require waiting for write to complete Because these registers are clocked by the system clock wri...

Page 575: ...Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify wri...

Page 576: ...eady 1 0 RO VALID 31 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write op...

Page 577: ...y on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 RO reserved 7 6 Seconds This field...

Page 578: ...d be preserved across a read modify write operation 0 RO reserved 30 27 Day of Week This field displays the day of the week in the encodings 0x0 to 0x6 The application defines which days are assigned...

Page 579: ...ield holds the day of the month value in hexadecimal Bits 4 0 correspond to hex values from 0x1 to 1F 1 to 31 days The value 0 is used to show an ignore match 0 RO DOM 4 0 579 June 18 2014 Texas Instr...

Page 580: ...across a read modify write operation 0 RO reserved 31 23 AM PM Designation This bit is used when CAL24 0 in the HIBCALCTL register Description Value AM 0 PM 1 0 WO AMPM 22 Software should not rely on...

Page 581: ...Field Seconds This field holds the seconds value in hexadecimal Bits 5 0 correspond to hex values from 0x0 to 0x3B 0 to 59 seconds 0 WO SEC 5 0 581 June 18 2014 Texas Instruments Production Data Tiva...

Page 582: ...ays are assigned to each encoding 0 WO DOW 26 24 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved a...

Page 583: ...y write operation 0 RO reserved 31 23 AM PM Designation This bit is used when CAL24 0 in the HIBCALCTL register Description Value AM 0 PM 1 0 RW AMPM 22 Software should not rely on the value of a rese...

Page 584: ...match value for seconds The value is represented in hexadecimal Bits 5 0 correspond to hex values from 0x0 to 0x3b 0 to 59 seconds To ignore the hours match write this field to all 1s 0 RW SEC 5 0 Jun...

Page 585: ...d RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DOM reserved RW RW RW RW RW RO RO RO RO RO RO RO RO RO RO RO Type 0 0...

Page 586: ...eturns 0x0000 0001 when locked otherwise the returned value is 0x0000 0000 unlocked Hibernation Lock HIBLOCK Base 0x400F C000 Offset 0x360 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27...

Page 587: ...2 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TPEN reserved TPCLR reserved MEMC...

Page 588: ...eld 0 W1C TPCLR 4 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write opera...

Page 589: ...registers are protected by the Hibernate HIBLOCK register HIB Tamper Status HIBTPSTAT Base 0x400F C000 Offset 0x404 Type RW1C reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserve...

Page 590: ...ld External Oscillator Failure Write a 1 to this bit to clear it Description Value External oscillator is valid 0 External oscillator has failed 1 0 RW1C XOSCFAIL 0 June 18 2014 590 Texas Instruments...

Page 591: ...HIB Tamper I O Control HIBTPIO Base 0x400F C000 Offset 0x410 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 EN2 LEV2 PUEN2 GFLTR2 reserved EN3 LEV3 PUEN3 GFLTR3 reserved RW...

Page 592: ...able for two hibernate clocks 0 A trigger match level is ignored until the TMPR2 signal is stable for 3 071 Hibernate Clocks 93 7ms using 32 768 kHz 1 0 RW GFLTR2 19 TMPR2 Internal Weak Pull up Enable...

Page 593: ...cription Value Detect disabled 0 Detect enabled 1 0 RW EN1 8 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be...

Page 594: ...R0 Trigger Level Description Value Trigger on level low 0 Trigger on level high 1 0 RW LEV0 1 TMPR0 Enable Description Value Detect disabled 0 Detect enabled 1 0 RW EN0 0 June 18 2014 594 Texas Instru...

Page 595: ...RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TIME RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0...

Page 596: ...et 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TRIG0 TRIG1 TRIG2 TRIG3 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Fie...

Page 597: ...n Value Default 0 A tamper event has been detected on TMPR 1 1 0 RO TRIG1 1 Status of TMPR 0 Trigger Description Value Default 0 A tamper event has been detected on TMPR 0 1 0 RO TRIG0 0 597 June 18 2...

Page 598: ...rved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide...

Page 599: ...RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibil...

Page 600: ...ontents of those blocks from being read by either the controller or by a debugger The TM4C1294NCPDT microcontroller provides enhanced performance and power savings by implementation of two sets of ins...

Page 601: ...Buffer Control FMPREn FMPPEn Flash Protection SRAM Control ROM Flash Array 2 Way Interleaved BOOTCFG USER_REGn User Registers Bus Matrix ROMSWMAP SCV RVP USRPWRUP FLPEKEY DMA SPB To Peripherals Boot R...

Page 602: ...e bank followed by a read of another bank can occur in successive clock cycles without incurring any delay However a write access that is followed immediately by a read access to the same bank incurs...

Page 603: ...ue and the EN bit in the BOOTCFG register is set the stack pointer and reset vector values are fetched from the beginning of flash This application stack pointer and reset vector are loaded and the pr...

Page 604: ...table and the final is the reverse polynomial table See the Tiva C Series TM4C129x ROM User s Guide literature number SPMU363 for more information on AES 8 2 2 4 Cyclic Redundancy Check CRC Error Det...

Page 605: ...efetch buffer It is recommended that code be compiled with switches set to eliminate literals as much as possible as a literal causes a flash access for that word and a stall for the wait states Most...

Page 606: ...it takes to execute Utilizing the four prefetch buffer configuration is the preferred method of configuration Figure 8 3 Single 256 Bit Prefetch Buffer Set WORD 7 WORD 6 WORD 5 WORD 4 WORD 3 WORD 2 W...

Page 607: ...resident in the prefetch buffers When an access does not hit in the prefetch buffer there is a delay that is incurred while the data is transferred from the Flash This delay is dependent on the progra...

Page 608: ...at 0xFC8 If the application sets the FPFON or FPFOFF bit while the CPU is currently reading or writing to Flash the prefetch buffer action of turning on or off happens only after the Flash operation...

Page 609: ...lication code Patches and updates can be done in this upper 512 KB of memory in the background while the lower 512 KB is being executed It is important to ensure that code offsets remain the same as t...

Page 610: ...of poorly behaving software during the development and debug phases The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks These settings create a policy...

Page 611: ...erasure or programming Read only is especially useful for utilities like the boot loader when the debug interface is permanently disabled In such combinations the boot loader which provides access con...

Page 612: ...s generated Note The DMA can access Flash in Run Mode only not available in low power modes 8 2 3 10 Flash Memory Programming The Tiva C Series devices provide a user friendly interface for Flash memo...

Page 613: ...rd aligned with Flash memory and therefore the register FWB0 corresponds with the address in FMA where bits 6 0 of FMA are all 0 FWB1 corresponds with the address in FMA 0x4 and so on Only the FWBn re...

Page 614: ...can only be returned to their factory default values of all 1s by performing the sequence described in Recovering a Locked Microcontroller on page 213 The mass erase of the main Flash memory array cau...

Page 615: ...MPPE14 FMPPE15 0x0000 0001F FMPPE15 USER_REG0 0x8000 0000 USER_REG0 USER_REG1 0x8000 0001 USER_REG1 USER_REG2 0x8000 0002 USER_REG2 USER_REG3 0x8000 0003 USER_REG3 FMD 0x7510 0000 BOOTCFG 8 2 4 EEPROM...

Page 616: ...s within the block Blocks are individually protectable Attempts to read from a block for which the application does not have permission return 0xFFFF FFFF Attempts to write into a block for which the...

Page 617: ...password registered with any block including block 0 allows for protection rules that control access of that block based on whether it is locked or unlocked Generally the lock can be used to prevent w...

Page 618: ...after the EEDONE register indicates a write has completed Interrupt Control The EEPROM module allows for an interrupt when a write completes to prevent the use of polling The interrupt can be used to...

Page 619: ...write the safe course of action is to retry the operation once the system is otherwise stable for example when the voltage is stabilized After the retry the control word and write data are advanced to...

Page 620: ...a result writing one word 500K times then trying to write a nearby word 500K times is not assured to work To ensure success the words should be written more in parallel All words can be written in a s...

Page 621: ...ion If the supply voltage is unstable when this return code is observed retrying the operation once the voltage is stabilized may clear the error The EEPROM initialization function code is named EEPRO...

Page 622: ...e 0x0000 03FF RO SSIZE 0xFC4 645 Flash Configuration Register 0x0000 0000 RW FLASHCONF 0xFC8 647 ROM Third Party Software 0x0000 0000 RO ROMSWMAP 0xFCC 649 Flash DMA Address Size 0x0000 0000 RW FLASHD...

Page 623: ...ection Read Enable 4 0xFFFF FFFF RW FMPRE4 0x210 669 Flash Memory Protection Read Enable 5 0xFFFF FFFF RW FMPRE5 0x214 669 Flash Memory Protection Read Enable 6 0xFFFF FFFF RW FMPRE6 0x218 669 Flash M...

Page 624: ...Program Enable 10 0xFFFF FFFF RW FMPPE10 0x428 671 Flash Memory Protection Program Enable 11 0xFFFF FFFF RW FMPPE11 0x42C 671 Flash Memory Protection Program Enable 12 0xFFFF FFFF RW FMPPE12 0x430 671...

Page 625: ...served RW RW RW RW RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 OFFSET RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 0 0...

Page 626: ...F D000 Offset 0x004 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 DATA RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4...

Page 627: ...21 22 23 24 25 26 27 28 29 30 31 WRKEY WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 WRITE ERASE MERASE COMT reserved...

Page 628: ...ess of that process Description Value A write of 0 has no effect on the state of this bit When read a 0 indicates that the previous mass erase access is complete 0 Set this bit to erase the Flash main...

Page 629: ...ead a 0 indicates that the previous write update access is complete 0 Set this bit to write the data stored in the FMD register into the Flash memory location specified by the contents of the FMA regi...

Page 630: ...odify write operation 0x0000 000 RO reserved 31 14 Program Verify Error Raw Interrupt Status Description Value An interrupt has not occurred 0 An interrupt is pending because the verify of a PROGRAM o...

Page 631: ...with future products the value of a reserved bit should be preserved across a read modify write operation 0 RO reserved 8 3 EEPROM Raw Interrupt Status This bit provides status EEPROM operation Descri...

Page 632: ...n was attempted on a block of Flash memory that contradicts the protection policy for that block as set in the FMPPEn registers 1 This status is sent to the interrupt controller when the AMASK bit in...

Page 633: ...odify write operation 0x0000 000 RO reserved 31 14 Program Verify Error Interrupt Mask Description Value The PROGRIS interrupt is suppressed and not sent to the interrupt controller 0 An interrupt is...

Page 634: ...ller 0 An interrupt is sent to the interrupt controller when the ERIS bit is set 1 0 RW EMASK 2 Programming Interrupt Mask This bit controls the reporting of the programming raw interrupt status to th...

Page 635: ...products the value of a reserved bit should be preserved across a read modify write operation 0x0000 000 RO reserved 31 14 PROGVER Masked Interrupt Status and Clear Description Value When read a 0 ind...

Page 636: ...a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 RO reserved 8 3 EEPROM Masked Interrupt Status and...

Page 637: ...n read a 1 indicates that an unmasked interrupt was signaled because a program or erase action was attempted on a block of Flash memory that contradicts the protection policy for that block as set in...

Page 638: ...y enable to initiate the appropriate access cycle for the location specified by the address in the FMA register If the KEY value in the BOOTCFG register is 0x0 at reset the value programmed in the FLP...

Page 639: ...ar the corresponding FWB n bit to preserve the existing data when the next write operation occurs Flash Write Buffer Valid FWBVAL Base 0x400F D000 Offset 0x030 Type RW reset 0x0000 0000 16 17 18 19 20...

Page 640: ...0x03C Type RO reset 0x0000 FFFF 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9...

Page 641: ...in FMA FWB1 is written to the address FMA 0x4 etc Note that only data bits that are 0 result in the Flash memory being modified A data bit that is 1 leaves the content of the Flash memory bit at its p...

Page 642: ...31 Prefetch Buffer Mode Description Value Single set of 2x256 bit buffers used 0 Two sets of 2x256 bit prefetch buffers are available to use and may be enabled through the FLASHCONF register 1 0x1 RO...

Page 643: ...EESS 22 19 Flash Sector Size of the physical bank Description Value 1 KB 0x0 2 KB 0x1 4 KB 0x2 8 KB 0x3 16 KB 0x4 reserved 0x5 0x7 0x4 RO MAINSS 18 16 Flash Size Indicates the size of the on chip Flas...

Page 644: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SIZE RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 Reset Description Reset Type Name...

Page 645: ...value of a reserved bit should be preserved across a read modify write operation 0 RO reserved 31 Flash Mirror Mode Enable Description Value Flash mirror mode is disabled 0 Flash mirror mode feature...

Page 646: ...scription Value No effect 0 Force prefetch buffers to be disabled 1 0 RW FPFOFF 16 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a...

Page 647: ...f a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x0 RO reserved 31 16 ROM SW Region 7 Availability D...

Page 648: ...ilable to the core 0x0 Region available to core 0x1 reserved 0x2 0x3 0x0 RO SW2EN 5 4 ROM SW Region 1 Availability Description Value Software region not available to the core 0x0 Region available to c...

Page 649: ...10 11 12 13 14 15 SIZE RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a rese...

Page 650: ...operation 0x0 RO reserved 31 29 Contains the starting address of the flash region accessible by DMA if the FLASHPP register DFA bit is set 0x0 RW ADDR 28 11 Software should not rely on the value of a...

Page 651: ...RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future pr...

Page 652: ...2 3 4 5 6 7 8 9 10 11 12 13 14 15 BLOCK RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the...

Page 653: ...FSET reserved RW RW RW RW RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit T...

Page 654: ...000 Offset 0x010 Type RW reset 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 VALUE RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VALUE RW RW RW RW...

Page 655: ...ement EERDWRINC Base 0x400A F000 Offset 0x014 Type RW reset 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 VALUE RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type Reset 0 1 2 3 4 5 6 7 8 9 10 11 1...

Page 656: ...f the following registers during the EEPROM initialization sequence are only valid when the WORKING bit is 0 in EEDONE register EERDWR or EERDWRINC EEPROT EEPASSn EEPROM Done Status EEDONE Base 0x400A...

Page 657: ...g for the EEPROM to copy to or from the copy buffer 1 0 RO WKCOPY 3 Working on an Erase Description Value The EEPROM is not erasing 0 A write is in progress and the original block is being erased afte...

Page 658: ...RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved ERETRY PRETRY reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0...

Page 659: ...NLOCK register If a multi word password is set and the number of words written is incorrect writing 0xFFFF FFFF to this register reverts the EEPROM lock to the locked state and the proper unlock seque...

Page 660: ...0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PROT ACC reserved RW RW RW RW RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit F...

Page 661: ...s not protected and is readable and writable at any time With password the block is readable but only writable when unlocked 0x0 With password the block is readable or writable only when unlocked This...

Page 662: ...e Based on whether 1 2 or all 3 registers have been written the unlock code also requires the same number of words to unlock Note Once the password is written the block is not actually locked until ei...

Page 663: ...O RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 INT reserved RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Rese...

Page 664: ...0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved Hn RO RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field H...

Page 665: ...0x054 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Hn RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11...

Page 666: ...e it reads as 0x0 The EEDONE register is set to 0x1 when the erase is started and changes to 0x0 or an error when the mass erase is complete EEPROM Debug Mass Erase EEDBGME Base 0x400A F000 Offset 0x0...

Page 667: ...the value of a reserved bit should be preserved across a read modify write operation 0x0 RO reserved 31 16 EEPROM Size Indicates the size of the on chip EEPROM Any values not shown are reserved Descri...

Page 668: ...e 0x400F E000 Offset 0x0D4 Type RO reset 0x0101 FFF0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RV RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Reset 0 1 2...

Page 669: ...lity Note Offset is relative to System Control base address of 0x400F E000 This register stores the read only protection bits for each 2 KB flash block FMPPEn stores the execute only bits Note that fo...

Page 670: ...26 27 28 29 30 31 READ_ENABLE RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 READ_ENABLE RW RW RW RW RW RW RW RW RW RW...

Page 671: ...sh Memory Protection Program Enable 10 FMPPE10 offset 0x428 Register 63 Flash Memory Protection Program Enable 11 FMPPE11 offset 0x42C Register 64 Flash Memory Protection Program Enable 12 FMPPE12 off...

Page 672: ...any other type of reset does not affect this register Once committed the only way to restore the factory default value of this register is to perform the Recover Locked Device sequence detailed in th...

Page 673: ...Enable Every eighth bit programs an 16 KB flash sector to be execute only The policies may be combined as shown in Table 8 2 on page 610 0xFFFF FFFF RW PROG_ENABLE 31 0 673 June 18 2014 Texas Instrum...

Page 674: ...ues out of the ROM Boot Loader 4 If there is data at address 0x0000 0004 that is not 0xFFFF FFFF the stack pointer SP is loaded from Flash memory at address 0x0000 0000 and the program counter PC is l...

Page 675: ...boot loader at reset Note The selected port can be reprogrammed for a different function after reset Description Value Port A 0x0 Port B 0x1 Port C 0x2 Port D 0x3 Port E 0x4 Port F 0x5 Port G 0x6 Port...

Page 676: ...t This bit chooses between using the value 0xA442 or the PEKEY value in the FLPEKEY register as the WRKEY value in the FMC FMC2 register Description Value The PEKEY value in the FLPEKEY register is co...

Page 677: ...n reset The only way to restore the factory default value of this register is to perform the Recover Locked Device sequence detailed in the JTAG section User Register n USER_REGn Base 0x400F E000 Offs...

Page 678: ...narios Ping pong for continuous data flow Scatter gather for a programmable list of up to 256 arbitrary transfers initiated from a single request Highly flexible and configurable channel operation Ind...

Page 679: ...erwise idle bus cycles the data transfer bandwidth it provides is essentially free with no impact on the rest of the system The bus architecture has been optimized to greatly enhance the ability of th...

Page 680: ...be used If multiple software requests in code are required then peripheral channel software requests should be used for proper DMA completion acknowledgement Table 9 1 DMA Channel Assignments Encoding...

Page 681: ...Reserved Reserved B Software SB B I2C4 TX B GPIO J SB UART7 TX B EPI 0 TX Software B GPTimer 1B 21 B I2C8 RX Reserved Reserved B Software SB B I2C5 RX B Software Reserved B Software SB UART1 RX 22 B...

Page 682: ...e checking for higher priority requests Therefore lower priority channels should not use a large arbitration size for best response on high priority channels The arbitration size can also be thought o...

Page 683: ...in this register the DMA controller only responds to burst requests for that channel 9 2 5 Channel Configuration The DMA controller uses an area of system memory to store a set of channel control str...

Page 684: ...t size Number of transfers before bus arbitration Total number of items to transfer Useburst flag Transfer mode The control word and each field are described in detail in DMA Channel Control Structure...

Page 685: ...nel is stopped manually If the NXTUSEBURST bit in the uDMA Channel Control Word DMACHCTL register is set while in BASIC mode and the XFERSIZE reaches 0x000 and is not written back transfers continue u...

Page 686: ...ER B Reload alternate structure DMA Controller Cortex M4F Processor Time Peripheral DMA Interrupt Peripheral DMA Interrupt SOURCE DEST CONTROL Unused SOURCE DEST CONTROL Unused SOURCE DEST CONTROL Unu...

Page 687: ...causing a peripheral action that results in a DMA request By programming the DMA controller using this method a set of up to 256 arbitrary transfers can be performed based on a single DMA request Ref...

Page 688: ...te control structure where it is executed by the DMA controller 4 The SRC and DST pointers in the task list must point to the last location in the corresponding buffer C 4 WORDS SRC A 16 WORDS SRC B S...

Page 689: ...imary control structure the DMA controller copies task B configuration to the channel s alternate control structure Then using the channel s alternate control structure the DMA controller copies data...

Page 690: ...Peripheral Scatter Gather mode This example shows a gather operation where data from three separate buffers in memory is copied to a single peripheral data register Figure 9 5 on page 691 shows how t...

Page 691: ...T TASK A TASK B TASK C Unused ITEMS 4 SRC Unused NOTES 1 Application has a need to copy data items from three separate locations in memory into a peripheral data register 2 Application sets up DMA tas...

Page 692: ...cture the DMA controller copies task B configuration to the channel s alternate control structure Then using the channel s alternate control structure the DMA controller copies data from the source bu...

Page 693: ...sent and a FIFO of data that has been received The uDMA controller is used to transfer data between these FIFOs and system memory For example when a UART FIFO contains one or more entries a single tr...

Page 694: ...transfer completion at the end of an entire transfer or when a FIFO or buffer reaches a certain level see Table 9 2 on page 682 and the individual peripheral chapters When a DMA transfer is complete...

Page 695: ...sts 4 Set bit 30 of the DMA Channel Request Mask Clear DMAREQMASKCLR register to allow the DMA controller to recognize requests for this channel 9 3 2 2 Configure the Channel Control Structure Now the...

Page 696: ...egister 2 Issue a transfer request by setting bit 30 of the DMA Channel Software Request DMASWREQ register The DMA transfer begins If the interrupt is enabled then the processor is notified by interru...

Page 697: ...the address of the source buffer 0x3F 2 Program the destination end pointer at offset 0x074 to the address of the peripheral s transmit FIFO register The control word at offset 0x078 must be programm...

Page 698: ...ontinuously receive 8 bit data from a peripheral into a pair of 64 byte buffers The peripheral has a receive FIFO with a trigger level of 8 The example peripheral uses DMA channel 8 9 3 4 1 Configure...

Page 699: ...ointer at offset 0x280 to the address of the peripheral s receive buffer 4 Program the alternate destination end pointer at offset 0x284 to the address of ping pong buffer B 0x3F The primary control w...

Page 700: ...ler makes transfers into buffer A using the primary channel control structure When the primary transfer to buffer A is complete it switches to the alternate channel control structure and makes transfe...

Page 701: ...in the channel control table are located in memory The DMA register addresses are given as a hexadecimal increment relative to the DMA base address of 0x400F F000 Note that the DMA module clock must b...

Page 702: ...ication 1 0x0000 00B2 RO DMAPeriphID1 0xFE4 735 DMA Peripheral Identification 2 0x0000 000B RO DMAPeriphID2 0xFE8 736 DMA Peripheral Identification 3 0x0000 0000 RO DMAPeriphID3 0xFEC 738 DMA PrimeCel...

Page 703: ...et 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ADDR RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ADDR RW RW RW RW RW RW RW RW RW RW RW RW RW RW...

Page 704: ...eset 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ADDR RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ADDR RW RW RW RW RW RW RW RW RW RW RW RW RW R...

Page 705: ...W RW RW Type 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 XFERMODE NXTUSEBURST XFERSIZE ARBSIZE RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type Reset Description Reset Type Name Bit Field...

Page 706: ...crement by 16 bit locations 0x1 Word Increment by 32 bit locations 0x2 No increment Address remains set to the value of the Source Address End Pointer DMASRCENDP for the channel 0x3 RW SRCINC 27 26 So...

Page 707: ...ion Value The access is non privileged 0 The access is privileged 1 0 RW SRCPROT0 18 Arbitration Size This field configures the number of transfers that can occur before the DMA controller re arbitrat...

Page 708: ...s to complete the transaction If this bit is set then the controller uses a burst transfer to complete the last transfer RW NXTUSEBURST 3 DMA Transfer Mode This field configures the operating mode of...

Page 709: ...pty The last task must have an XFERMODE value other than 0x5 Note that for continuous operation the last task can update the primary channel control structure back to the start of the list or to anoth...

Page 710: ...ual to the number of DMA channels the DMA controller is configured to use minus one The value of 0x1F corresponds to 32 DMA channels 0x1F RO DMACHANS 20 16 Software should not rely on the value of a r...

Page 711: ...e Name Bit Field Master Enable Status Description Value The DMA controller is disabled 0 The DMA controller is enabled 1 0 RO MASTEN 0 711 June 18 2014 Texas Instruments Production Data Tiva TM4C1294N...

Page 712: ...11 12 13 14 15 MASTEN reserved WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO Type Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide comp...

Page 713: ...set 0x008 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ADDR RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9...

Page 714: ...ointer DMAALTBASE Base 0x400F F000 Offset 0x00C Type RO reset 0x0000 0200 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ADDR RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0...

Page 715: ...AT Base 0x400F F000 Offset 0x010 Type RO reset 0x03C3 CF00 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 WAITREQ n RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0...

Page 716: ...WO WO WO WO WO WO WO WO WO Type Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SWREQ n WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO Type Reset Description Reset Type Name Bit Field Channel n Software...

Page 717: ...set if the corresponding peripheral does not support the burst request model Refer to Request Types on page 682 for more details about request types DMA Channel Useburst Set DMAUSEBURSTSET Base 0x400...

Page 718: ...2 23 24 25 26 27 28 29 30 31 CLR n WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO Type Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLR n WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO Type Reset Des...

Page 719: ...T n RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SET n RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 0 0 0 0...

Page 720: ...6 27 28 29 30 31 CLR n WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO Type Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLR n WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO Type Reset Description Res...

Page 721: ...9 20 21 22 23 24 25 26 27 28 29 30 31 SET n RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SET n RW RW RW RW RW RW RW...

Page 722: ...WO WO WO WO WO WO WO WO WO WO WO WO WO WO Type Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLR n WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO Type Reset Description Reset Type Name Bit Field Clear...

Page 723: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SET n RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name...

Page 724: ...WO WO WO Type Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLR n WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO Type Reset Description Reset Type Name Bit Field Channel n Alternate Clear Description V...

Page 725: ...W RW RW RW RW RW RW RW RW RW RW RW RW RW Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SET n RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 0 0 0 0 0 0 0 0 0 0...

Page 726: ...3 24 25 26 27 28 29 30 31 CLR n WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO Type Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLR n WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO Type Reset Descri...

Page 727: ...RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ERRCLR reserved RW1C RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0...

Page 728: ...bit reads as 0 if the corresponding DMACHMAPn register field value is equal to 0 otherwise it reads as 1 if the corresponding DMACHMAPn register field value is not equal to 0 DMA Channel Assignment DM...

Page 729: ...RW Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field DMA Channel 7 Source Select See Table 9 1 on page 680 for channel assignments 0x00 RW CH7SEL 31 28 DMA Channel 6 So...

Page 730: ...RW Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field DMA Channel 15 Source Select See Table 9 1 on page 680 for channel assignments 0x00 RW CH15SEL 31 28 DMA Channel 14...

Page 731: ...Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field DMA Channel 23 Source Select See Table 9 1 on page 680 for channel assignments 0x00 RW CH23SEL 31 28 DMA Channel 22 Sou...

Page 732: ...W Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field DMA Channel 31 Source Select See Table 9 1 on page 680 for channel assignments 0x00 RW CH31SEL 31 28 DMA Channel 30 S...

Page 733: ...0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PID0 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Softw...

Page 734: ...0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PID1 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 1 0 0 1 1 0 1 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Soft...

Page 735: ...0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PID2 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Softwa...

Page 736: ...0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PID3 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Soft...

Page 737: ...0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PID4 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Sof...

Page 738: ...0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CID0 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Softw...

Page 739: ...0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CID1 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software...

Page 740: ...0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CID2 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Soft...

Page 741: ...0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CID3 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Softwa...

Page 742: ...Programmable control for GPIO interrupts Interrupt generation masking Edge triggered on rising falling or both Level sensitive on High or Low values Per pin interrupts available on Port P and Port Q...

Page 743: ...ition a Power On Reset POR returns these GPIO to their original special consideration state Table 10 1 GPIO Pins With Special Considerations GPIOCR GPIOPCTL GPIOPUR GPIOPDR GPIODEN GPIOAFSEL Default R...

Page 744: ...5 TCK SWCLK 100 PC0 TMS SWDIO 99 PC1 TDI 98 PC2 TDO SWO 97 PC3 EPI0S7 U7Rx C1 25 PC4 EPI0S6 RTCCLK U7Tx C1 24 PC5 EPI0S5 U5Rx C0 23 PC6 EPI0S4 U5Tx C0 22 PC7 SSI2XDAT1 C0o T0CCP0 I2C7SCL AIN15 1 PD0 S...

Page 745: ...1 EPI0S2 U4RTS AIN18 20 PK2 EPI0S3 U4CTS AIN19 21 PK3 EPI0S32 M0PWM6 EN0LED0 I2C3SCL 63 PK4 EPI0S31 M0PWM7 EN0LED2 I2C3SDA 62 PK5 EPI0S25 M0FAULT1 EN0LED1 I2C4SCL 61 PK6 EPI0S24 M0FAULT2 RTCCLK I2C4SD...

Page 746: ...s that are shaded gray are the power on default values for the corresponding GPIO pin Encodings 9 10 and 12 are not used on this device 10 2 Pad Capabilities There are two main types of pads provided...

Page 747: ...are functions refer to Table 26 5 on page 1808 Figure 10 1 Digital I O Pads MUX MUX MUX Pad Control Commit Control Data Control Interrupt Control DEMUX Digital I O Pad Identification Registers GPIOPer...

Page 748: ...registers allow software to configure the operational modes of the GPIOs The data direction register configures the GPIO as an input or an output while the data register either captures incoming data...

Page 749: ...TA register covers 256 locations in the memory map During a write if the address bit associated with that data bit is set the value of the GPIODATA register is altered If the address bit is cleared th...

Page 750: ...ge detect interrupt the RIS bit in the GPIORIS register is cleared by writing a 1 to the corresponding bit in the GPIO Interrupt Clear GPIOICR register see page 769 The corresponding GPIOMIS bit refle...

Page 751: ...ion oscillator 2 Write any data to be retained during power cut to the HIBDATA register at offsets 0x030 0x06F 3 Configure the GPIOWAKEPEN and GPIOWAKELVL registers at offsets 0x540 and 0x544 in the G...

Page 752: ...lows GPIODR2R GPIODR4R GPIODR8R GPIODR12R GPIOSLR and GPIOODR Note Port pins PM 7 4 operate as Fast GPIO pads but support only 2 4 6 and 8 mA drive capability 10 and 12 mA drive are not supported All...

Page 753: ...e SCGCGPIO and DCGCGPIO registers can be programmed in the same manner to enable clocking in Sleep and Deep Sleep modes 2 Set the direction of the GPIO port pins by programming the GPIODIR register A...

Page 754: ...GPIOIM register 11 Optionally software can lock the configurations of the NMI and JTAG SWD pins on the GPIO port pins by setting the LOCK bits in the GPIOLOCK register When the internal POR signal is...

Page 755: ...ed 1 not masked GPIOIM a X Ignored don t care bit 10 5 Register Map Table 10 7 on page 757 lists the GPIO registers Important The GPIO registers in this chapter are duplicated in each GPIO block howev...

Page 756: ...control registers provide a layer of protection against accidental programming of critical hardware signals including the GPIO pins that can function as JTAG SWD signals and the NMI signal The commit...

Page 757: ...0C 776 GPIO Pull Up Select RW GPIOPUR 0x510 778 GPIO Pull Down Select 0x0000 0000 RW GPIOPDR 0x514 780 GPIO Slew Rate Control Select 0x0000 0000 RW GPIOSLR 0x518 781 GPIO Digital Enable RW GPIODEN 0x5...

Page 758: ...809 GPIO Peripheral Identification 2 0x0000 0018 RO GPIOPeriphID2 0xFE8 810 GPIO Peripheral Identification 3 0x0000 0001 RO GPIOPeriphID3 0xFEC 811 GPIO PrimeCell Identification 0 0x0000 000D RO GPIOP...

Page 759: ...0x4005 D000 GPIO Port G AHB base 0x4005 E000 GPIO Port H AHB base 0x4005 F000 GPIO Port J AHB base 0x4006 0000 GPIO Port K AHB base 0x4006 1000 GPIO Port L AHB base 0x4006 2000 GPIO Port M AHB base 0...

Page 760: ...PIO Port M AHB base 0x4006 3000 GPIO Port N AHB base 0x4006 4000 GPIO Port P AHB base 0x4006 5000 GPIO Port Q AHB base 0x4006 6000 Offset 0x400 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25...

Page 761: ...base 0x4005 E000 GPIO Port H AHB base 0x4005 F000 GPIO Port J AHB base 0x4006 0000 GPIO Port K AHB base 0x4006 1000 GPIO Port L AHB base 0x4006 2000 GPIO Port M AHB base 0x4006 3000 GPIO Port N AHB ba...

Page 762: ...t D AHB base 0x4005 B000 GPIO Port E AHB base 0x4005 C000 GPIO Port F AHB base 0x4005 D000 GPIO Port G AHB base 0x4005 E000 GPIO Port H AHB base 0x4005 F000 GPIO Port J AHB base 0x4006 0000 GPIO Port...

Page 763: ...IO Port L AHB base 0x4006 2000 GPIO Port M AHB base 0x4006 3000 GPIO Port N AHB base 0x4006 4000 GPIO Port P AHB base 0x4006 5000 GPIO Port Q AHB base 0x4006 6000 Offset 0x40C Type RW reset 0x0000 000...

Page 764: ...HB base 0x4006 6000 Offset 0x410 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 765: ...05 B000 GPIO Port E AHB base 0x4005 C000 GPIO Port F AHB base 0x4005 D000 GPIO Port G AHB base 0x4005 E000 GPIO Port H AHB base 0x4005 F000 GPIO Port J AHB base 0x4006 0000 GPIO Port K AHB base 0x4006...

Page 766: ...terrupt condition has occurred on the corresponding pin 1 For edge detect interrupts this bit is cleared by writing a 1 to the corresponding bit in the GPIOICR register For a GPIO level detect interru...

Page 767: ...6 0000 GPIO Port K AHB base 0x4006 1000 GPIO Port L AHB base 0x4006 2000 GPIO Port M AHB base 0x4006 3000 GPIO Port N AHB base 0x4006 4000 GPIO Port P AHB base 0x4006 5000 GPIO Port Q AHB base 0x4006...

Page 768: ...tion on the corresponding pin has triggered an interrupt to the interrupt controller 1 For edge detect interrupts this bit is cleared by writing a 1 to the corresponding bit in the GPIOICR register Fo...

Page 769: ...AHB base 0x4006 2000 GPIO Port M AHB base 0x4006 3000 GPIO Port N AHB base 0x4006 4000 GPIO Port P AHB base 0x4006 5000 GPIO Port Q AHB base 0x4006 6000 Offset 0x41C Type W1C reset 0x0000 0000 16 17...

Page 770: ...tion against accidental programming of critical hardware signals including the GPIO pins that can function as JTAG SWD signals and the NMI signal The commit control process must be followed for these...

Page 771: ...00 GPIO Port L AHB base 0x4006 2000 GPIO Port M AHB base 0x4006 3000 GPIO Port N AHB base 0x4006 4000 GPIO Port P AHB base 0x4006 5000 GPIO Port Q AHB base 0x4006 6000 Offset 0x420 Type RW reset 16 17...

Page 772: ...AHB base 0x4006 4000 GPIO Port P AHB base 0x4006 5000 GPIO Port Q AHB base 0x4006 6000 Offset 0x500 Type RW reset 0x0000 00FF 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO R...

Page 773: ...0 GPIO Port P AHB base 0x4006 5000 GPIO Port Q AHB base 0x4006 6000 Offset 0x504 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO...

Page 774: ...e 0x4006 0000 GPIO Port K AHB base 0x4006 1000 GPIO Port L AHB base 0x4006 2000 GPIO Port M AHB base 0x4006 3000 GPIO Port N AHB base 0x4006 4000 GPIO Port P AHB base 0x4006 5000 GPIO Port Q AHB base...

Page 775: ...ase 0x4005 8000 GPIO Port B AHB base 0x4005 9000 GPIO Port C AHB base 0x4005 A000 GPIO Port D AHB base 0x4005 B000 GPIO Port E AHB base 0x4005 C000 GPIO Port F AHB base 0x4005 D000 GPIO Port G AHB bas...

Page 776: ...gister The GPIO commit control registers provide a layer of protection against accidental programming of critical hardware signals including the GPIO pins that can function as JTAG SWD signals and the...

Page 777: ...Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PUE reserved RW RW RW RW RW RW RW RW RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on t...

Page 778: ...inst accidental programming of critical hardware signals including the GPIO pins that can function as JTAG SWD signals and the NMI signal The commit control process must be followed for these pins eve...

Page 779: ...RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PDE reserved RW RW RW RW RW RW RW RW RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Des...

Page 780: ...2000 GPIO Port M AHB base 0x4006 3000 GPIO Port N AHB base 0x4006 4000 GPIO Port P AHB base 0x4006 5000 GPIO Port Q AHB base 0x4006 6000 Offset 0x518 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23...

Page 781: ...ng it by setting the GPIOCR register The GPIO commit control registers provide a layer of protection against accidental programming of critical hardware signals including the GPIO pins that can functi...

Page 782: ...RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DEN reserved RW RW RW RW RW RW RW RW RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 Res...

Page 783: ...base 0x4006 0000 GPIO Port K AHB base 0x4006 1000 GPIO Port L AHB base 0x4006 2000 GPIO Port M AHB base 0x4006 3000 GPIO Port N AHB base 0x4006 4000 GPIO Port P AHB base 0x4006 5000 GPIO Port Q AHB b...

Page 784: ...e this protection is currently only implemented on the NMI and JTAG SWD pins see Signal Tables on page 1772 for pin numbers all of the other bits in the GPIOCR registers cannot be written with 0x0 The...

Page 785: ...six pins are the only GPIOs that are protected by the GPIOCR register Because of this the register type for the corresponding GPIO Ports is RW The default reset value for the GPIOCR register is 0x0000...

Page 786: ...6 2000 GPIO Port M AHB base 0x4006 3000 GPIO Port N AHB base 0x4006 4000 GPIO Port P AHB base 0x4006 5000 GPIO Port Q AHB base 0x4006 6000 Offset 0x528 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 2...

Page 787: ...tion GPIO pins Most GPIO pins are configured as GPIOs and tri stated by default GPIOAFSEL 0 GPIODEN 0 GPIOPDR 0 GPIOPUR 0 and GPIOPCTL 0 Special consideration pins may be programed to a non GPIO funct...

Page 788: ...1 12 13 14 15 PMC0 PMC1 PMC2 PMC3 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type Reset Description Reset Type Name Bit Field Port Mux Control 7 This field controls the configuration for GPIO pin...

Page 789: ...AHB base 0x4006 3000 GPIO Port N AHB base 0x4006 4000 GPIO Port P AHB base 0x4006 5000 GPIO Port Q AHB base 0x4006 6000 Offset 0x530 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29...

Page 790: ...0x4006 6000 Offset 0x534 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0...

Page 791: ...5 SUM reserved RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit...

Page 792: ...RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DRV12 reserved RW RW RW RW RW RW RW RW RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0...

Page 793: ...t M AHB base 0x4006 3000 GPIO Port N AHB base 0x4006 4000 GPIO Port P AHB base 0x4006 5000 GPIO Port Q AHB base 0x4006 6000 Offset 0x540 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 2...

Page 794: ...Value Wake on level is not enabled 0 Wake on level is enabled 1 0 RW WAKEP4 4 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a rese...

Page 795: ...GPIO Port M AHB base 0x4006 3000 GPIO Port N AHB base 0x4006 4000 GPIO Port P AHB base 0x4006 5000 GPIO Port Q AHB base 0x4006 6000 Offset 0x544 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 2...

Page 796: ...Value Wake level low 0 Wake level high 1 0 RW WAKELVL4 4 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be pre...

Page 797: ...et 0x548 Type RO reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8...

Page 798: ...Description Value Pin is not wake up source 0 Pin wake event asserted to hibernate module 1 0 RO STAT4 4 Software should not rely on the value of a reserved bit To provide compatibility with future p...

Page 799: ...16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 EDE reserved...

Page 800: ...l 2 mA any bits set in the GPIODR8R add an extra 4 mA of drive The GPIODR12R register is only valid when the EDMn value is 0x3 For this encoding setting a bit in the GPIODR12R register adds 4 mA of dr...

Page 801: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved b...

Page 802: ...d Write one clear other behavior of GPIODDRnR registers is disabled A 2 mA driver is always enabled setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R reg...

Page 803: ...O Port L AHB base 0x4006 2000 GPIO Port M AHB base 0x4006 3000 GPIO Port N AHB base 0x4006 4000 GPIO Port P AHB base 0x4006 5000 GPIO Port Q AHB base 0x4006 6000 Offset 0xFD0 Type RO reset 0x0000 0000...

Page 804: ...Port L AHB base 0x4006 2000 GPIO Port M AHB base 0x4006 3000 GPIO Port N AHB base 0x4006 4000 GPIO Port P AHB base 0x4006 5000 GPIO Port Q AHB base 0x4006 6000 Offset 0xFD4 Type RO reset 0x0000 0000...

Page 805: ...Port L AHB base 0x4006 2000 GPIO Port M AHB base 0x4006 3000 GPIO Port N AHB base 0x4006 4000 GPIO Port P AHB base 0x4006 5000 GPIO Port Q AHB base 0x4006 6000 Offset 0xFD8 Type RO reset 0x0000 0000...

Page 806: ...Port L AHB base 0x4006 2000 GPIO Port M AHB base 0x4006 3000 GPIO Port N AHB base 0x4006 4000 GPIO Port P AHB base 0x4006 5000 GPIO Port Q AHB base 0x4006 6000 Offset 0xFDC Type RO reset 0x0000 0000 1...

Page 807: ...Port M AHB base 0x4006 3000 GPIO Port N AHB base 0x4006 4000 GPIO Port P AHB base 0x4006 5000 GPIO Port Q AHB base 0x4006 6000 Offset 0xFE0 Type RO reset 0x0000 0061 16 17 18 19 20 21 22 23 24 25 26...

Page 808: ...Port M AHB base 0x4006 3000 GPIO Port N AHB base 0x4006 4000 GPIO Port P AHB base 0x4006 5000 GPIO Port Q AHB base 0x4006 6000 Offset 0xFE4 Type RO reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 2...

Page 809: ...Port M AHB base 0x4006 3000 GPIO Port N AHB base 0x4006 4000 GPIO Port P AHB base 0x4006 5000 GPIO Port Q AHB base 0x4006 6000 Offset 0xFE8 Type RO reset 0x0000 0018 16 17 18 19 20 21 22 23 24 25 26 2...

Page 810: ...ort M AHB base 0x4006 3000 GPIO Port N AHB base 0x4006 4000 GPIO Port P AHB base 0x4006 5000 GPIO Port Q AHB base 0x4006 6000 Offset 0xFEC Type RO reset 0x0000 0001 16 17 18 19 20 21 22 23 24 25 26 27...

Page 811: ...Port M AHB base 0x4006 3000 GPIO Port N AHB base 0x4006 4000 GPIO Port P AHB base 0x4006 5000 GPIO Port Q AHB base 0x4006 6000 Offset 0xFF0 Type RO reset 0x0000 000D 16 17 18 19 20 21 22 23 24 25 26...

Page 812: ...Port M AHB base 0x4006 3000 GPIO Port N AHB base 0x4006 4000 GPIO Port P AHB base 0x4006 5000 GPIO Port Q AHB base 0x4006 6000 Offset 0xFF4 Type RO reset 0x0000 00F0 16 17 18 19 20 21 22 23 24 25 26 2...

Page 813: ...Port M AHB base 0x4006 3000 GPIO Port N AHB base 0x4006 4000 GPIO Port P AHB base 0x4006 5000 GPIO Port Q AHB base 0x4006 6000 Offset 0xFF8 Type RO reset 0x0000 0005 16 17 18 19 20 21 22 23 24 25 26 2...

Page 814: ...Port M AHB base 0x4006 3000 GPIO Port N AHB base 0x4006 4000 GPIO Port P AHB base 0x4006 5000 GPIO Port Q AHB base 0x4006 6000 Offset 0xFFC Type RO reset 0x0000 00B1 16 17 18 19 20 21 22 23 24 25 26 2...

Page 815: ...e levels on the internal Non Blocking Read FIFO NBRFIFO Write channel request asserted by empty on the internal Write FIFO WFIFO The EPI supports three primary functional modes Synchronous Dynamic Ran...

Page 816: ...iRDY signal provided for stall capability of reads and writes Manual chip enable or use extra address pins General Purpose mode Wide parallel interfaces for fast communications with CPLDs and FPGAs Da...

Page 817: ...s the encoding that must be programmed into the PMCn field in the GPIO Port Control GPIOPCTL register page 787 to assign the EPI signals to the specified GPIO port pins For more information on configu...

Page 818: ...TTL I O PP2 15 PN2 15 103 109 EPI0S29 EPI module 0 signal 30 TTL I O PP3 15 PN3 15 104 110 EPI0S30 EPI module 0 signal 31 TTL I O PK5 15 62 EPI0S31 EPI module 0 signal 32 TTL I O PK4 15 63 EPI0S32 EP...

Page 819: ...in the Host Bus multi chip select mode when they are used to enable the different chip selects If the NBRFIFO is filled then the reads pause until space is made available The NBRFIFO can be configured...

Page 820: ...o 0x4 and the application bursts four words to an empty FIFO the WRFIFO trigger may or may not deassert depending on if all four words were written to the WRFIFO or if the first word was passed immedi...

Page 821: ...Map EPIADDRMAP register The selected start address and range is dependent on the type of external device and maximum address as appropriate For example for a 512 megabit SDRAM program the ERADR field...

Page 822: ...or refresh value other than the default value it is important to configure the FREQ and RFSH fields in the EPI SDRAM Configuration EPISDRAMCFG register shortly after activating the mode After the 100...

Page 823: ...2 A12 b EPI0S12 D13 BA0 EPI0S13 D14 BA1 EPI0S14 D15 EPI0S15 DQML EPI0S16 DQMH EPI0S17 CASn EPI0S18 RASn EPI0S19 not used EPI0S20 EPI0S27 WEn EPI0S28 CSn EPI0S29 CKE EPI0S30 CLK EPI0S31 a If two signal...

Page 824: ...as SysClk However if SysClk is running at higher speeds the bus interface can run only as fast as half speed and the COUNT0 field must be configured to at least 0x0001 11 4 2 4 Non Blocking Read Cycle...

Page 825: ...6 shows a write cycle of n halfwords n can be any number greater than or equal to 1 The cycle begins with the Activate command and the row address on the EPI0S 15 0 signals With the programmed CAS lat...

Page 826: ...l Host Bus accesses have an address phase followed by a data phase The ALE indicates to an external latch to capture the address then hold it until the data phase The polarity of the ALE can be active...

Page 827: ...LE and EPI0S27 is used as CSn 0x4 Quad CSn Configuration EPI0S30 is used as CS0n and EPI0S27 is used as CS1n EPI0S34 is used as CS2n and EPI0S33 is used as CS3n 0x5 ALE with Quad CSn Configuration EPI...

Page 828: ...chip select N A N A ERADR defined address range 0x6000 000 or 0x8000 000 ECADR defined address range 0x1000 000 0x1 0x0 0x1 or 0x2 Dual chip select 0xC000 0000 0xA000 0000 0x8000 0000 0x6000 0000 0x0...

Page 829: ...ies the available address space is doubled For example 28 bits of address accesses 512 MB in this mode Table 11 7 on page 829 shows the capabilities of the HB8 and HB16 modes as well as the available...

Page 830: ...10 bits a No 0 2 0x3 0 0x1 HB16 512 B 8 bits b Yes 1 2 0x3 0 0x1 HB16 4 kB 11 bits a No 0 1 0x0 1 0x1 HB16 1 kB 9 bits b Yes 1 1 0x0 1 0x1 HB16 4 kB 11 bits a No 0 4 0x1 1 0x1 HB16 1 kB 9 bits b Yes...

Page 831: ...O HB8 Signal MODE ADNOMUX Cont Read HB8 Signal MODE ADMUX CSCFG EPI Signal D0 D0 AD0 X a EPI0S0 D1 D1 AD1 X EPI0S1 D2 D2 AD2 X EPI0S2 D3 D3 AD3 X EPI0S3 D4 D4 AD4 X EPI0S4 D5 D5 AD5 X EPI0S5 D6 D6 AD6...

Page 832: ...CS0n 0x4 CS1n CS1n 0x5 0x6 RDn RDn OEn RDn OEn X EPI0S28 WRn WRn WRn X EPI0S29 ALE ALE 0x0 EPI0S30 CSn CSn CSn 0x1 CS0n CS0n CS0n 0x2 ALE ALE 0x3 0x4 CS0n CS0n 0x5 ALE ALE 0x6 Clock c Clock c Clock c...

Page 833: ...are used as configured by the BSEL bit in the EPIHB16CFG register Although the EPI0S31 signal can be configured for the EPI clock signal in Host Bus mode it is not required and should be configured a...

Page 834: ...1 X X EPI0S21 A6 A22 X X EPI0S22 A7 A23 0 X c EPI0S23 1 A8 A24 0 0x0 EPI0S24 1 0 0x1 1 0 0x2 1 0 0x3 BSEL0n BSEL0n 1 A8 A24 0 0x4 1 0 0x5 1 0 0x6 BSEL0n BSEL0n 1 A9 A25 X 0x0 EPI0S25 0x1 CS1n A9 A25 0...

Page 835: ...0S28 WRn WRn WRn X X EPI0S29 ALE ALE X 0x0 EPI0S30 CSn CSn CSn X 0x1 CS0n CS0n CS0n X 0x2 ALE ALE X 0x3 ALE ALE X 0x4 CS0n CS0n X 0x5 ALE ALE X 0x6 Clock d Clock d Clock d X X EPI0S31 iRDY iRDY iRDY X...

Page 836: ...E IRDYDLY 11 IRDYDLY 01 IRDYDLY 10 Data F Data A Data B Data C Data D Data E Data A Data B Data C Data D Data E Data A Data B Data C Data D Data E Figure 11 6 iRDY Signal Connection WAIT WAIT Other D...

Page 837: ...in the EPICFG register to 0x13 Choose between an integer or formula clock divide for the baud rate by configuring the INTDIV bit in the EPICFG register 3 Configure the EPIBAUD register to the desired...

Page 838: ...to read and write The WAIT iRDY pin stalls the access for the duration of the latency and adds cycles if there is a refresh collision To get the best performance set CR 13 11 0x2 the WRWS field of th...

Page 839: ...Dn WRn EPI0S29 iRDY EPI0S32 EPI0S 15 0 BSELn ADDRESS Figure 11 8 PSRAM Burst Write Latency 3 clocks DATA0 DATA1 DATA2 DATA3 EPICLK EPI0S31 EPI0S 19 0 ALE CSn OEn EPI0S28 WRn EPI0S29 iRDY EPI0S32 EPI0S...

Page 840: ...re 11 9 on page 840 and Figure 11 10 on page 841 depict the delay in data transfer during a refresh collision Figure 11 9 Read Delay During Refresh Event DATA0 DATA1 DATA2 DATA3 ADDRESS BSELn EPICLK E...

Page 841: ...igure 11 11 on page 842 shows how to connect the EPI signals to a 16 bit SRAM and a 16 bit Flash memory with muxed address and memory using byte selects and dual chip selects with ALE This schematic i...

Page 842: ...EPI13 EPI14 EPI15 EPI30 3 3V GND GND A 0 15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A 0 15 EPI_16_BUS EPI_16_BUS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 EPI16 EPI17 EPI0 E...

Page 843: ...he EPI controller supports four variants of the Host Bus model using 8 or 16 bits of data in all four cases The four sub modes are selected using the MODE bits in the EPIHBnCFG register and are 1 Addr...

Page 844: ...enerally not enough address bits available Writes are not permitted in this mode 4 FIFO mode uses 8 or 16 bits of data removes ALE and address pins and optionally adds external XFIFO FULL EMPTY flag i...

Page 845: ...0 CSn EPI0S30 WRn EPI0S29 RDn OEn EPI0S28 Address Data BSEL0n BSEL1na a BSEL0n and BSEL1n are available in Host Bus 16 mode only Figure 11 14 on page 846 shows a write cycle with the address and data...

Page 846: ...e 11 15 Host Bus Write Cycle with Multiplexed Address and Data and ALE with Dual or Quad CSn Data ALE EPI0S30 CS0n CS1n CS2n CS3n EPI0S26 EPI0S27 EPIOS34 EPIOS33 WRn EPI0S29 RDn OEn EPI0S28 Address hi...

Page 847: ...0 WRn EPI0S29 RDn EPI0S28 Data Data Data Figure 11 18 Two Entry FIFO FFULL EPI0S27 FEMPTY EPI0S26 CSn EPI0S30 WRn EPI0S29 RDn EPI0S28 Data Data Data Data 11 4 4 General Purpose Mode The General Purpos...

Page 848: ...is taking place and if any transaction is taking place Separation of address request and data phases may be used on writes using the WR2CYC bit in the EPIGPCFG register This configuration allows the...

Page 849: ...may be further delayed by the bus due to DMA or draining of a previous write With both GPIO and the EPI controller reads may be performed directly in which case the current pin states are read back Wi...

Page 850: ...this mode half word accesses are used AO is the LSB of the address and is equivalent to the system A1 address b In this mode word accesses are used AO is the LSB of the address and is equivalent to th...

Page 851: ...Addr3 Data2 Data1 Data3 FRAME Signal Operation The operation of the FRAME signal is controlled by the FRMCNT and FRM50 bits When FRM50 is clear the FRAME signal is high whenever the WR or RD strobe i...

Page 852: ...T see Figure 11 24 on page 852 Figure 11 24 FRAME Signal Operation FRM50 0 and FRMCNT 2 Clock EPI0S31 Frame EPI0S30 RD EPI0S29 WR EPI0S28 When FRM50 is set the FRAME signal transitions on the rising e...

Page 853: ...ode is enabled If CLKGATE is set the clock is output only when a transaction is occurring otherwise the clock is held high If the WR2CYC bit is clear the EPI clock begins toggling 1 cycle before the W...

Page 854: ...e accesses to registers are supported Table 11 13 External Peripheral Interface EPI Register Map See page Description Reset Type Name Offset 857 EPI Configuration 0x0000 0000 RW EPICFG 0x000 859 EPI M...

Page 855: ...t Status 0x0000 0004 RO EPIRIS 0x214 911 EPI Masked Interrupt Status 0x0000 0000 RO EPIMIS 0x218 913 EPI Error and Interrupt Status and Clear 0x0000 0000 RW1C EPIEISC 0x21C 915 EPI Host Bus 8 Configur...

Page 856: ...11 6 Register Descriptions This section lists and describes the EPI registers in numerical order by address offset June 18 2014 856 Texas Instruments Production Data External Peripheral Interface EPI...

Page 857: ...KEN reserved INTDIV reserved RW RW RW RW RW RO RO RO RW RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a...

Page 858: ...the EPISDRAMCFG register 0x1 8 Bit Host Bus HB8 Host bus 8 bit interface also known as the MCU interface Control address and data pins are configured using the EPIHB8CFG and EPIHB8CFG2 registers 0x2 1...

Page 859: ...is not a straight divider or count The EPI Clock on EPI0S31 is related to the COUNTn field and the system clock as follows If COUNTn 0 kFreq SystemCloc eq EPIClockFr otherwise 2 1 2 COUNTn kFreq Syste...

Page 860: ...bit is set in the EPIHBnCFG2 register This bit field contains a counter used to divide the system clock by the count A count of 0 means the system clock is used as is 0x0000 RW COUNT1 31 16 Baud Rate...

Page 861: ...follows If COUNTn 0 kFreq SystemCloc eq EPIClockFr otherwise 2 1 2 COUNTn kFreq SystemCloc eq EPIClockFr where the symbol around COUNTn 2 is the floor operator meaning the largest integer less than o...

Page 862: ...ount of 0 means the system clock is unchanged This bit field is only valid when quad chip selects are enabled by setting the CSCFGEXT to 1 and the CSCFG field to 0x1 or 0x2 In addition the CSBAUD bit...

Page 863: ...15 SIZE reserved SLEEP reserved RW RW RO RO RO RO RO RO RO RW RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field EPI Frequency Range This field configur...

Page 864: ...ate but is self refreshed 1 0 RW SLEEP 9 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a...

Page 865: ...out the use of ALE If an alternative to chip selects are required a chip enable can be handled in one of three ways 1 Manually control via GPIOs 2 Associate one or more upper address pins to CE Becaus...

Page 866: ...Invert EPI clock to ensure the rising edge is centered for outbound signal s setup and hold Inbound signal is captured on rising edge EPI clock 1 0 RW CLKINV 29 Input Ready Enable Description Value N...

Page 867: ...ty Description Value The address latch strobe for CS0n accesses is ALEn active Low 0 The address latch strobe for CS0n accesses is ALE active High 1 1 RW ALEHIGH 19 Software should not rely on the val...

Page 868: ...adds wait states to the data phase of CS0n the address phase is not affected The effect is to delay the rising edge of RDn Oen or the falling edge of RD Each wait state adds 2 EPI clock cycles to the...

Page 869: ...e chip select option is enabled and CSBAUD is clear all chip selects use the MODE encoding programmed in this register Description Value ADMUX AD 7 0 Data and Address are muxed 0x0 ADNONMUX D 7 0 Data...

Page 870: ...ithout the use of ALE If an alternative to chip selects are required a chip enable can be handled in one of three ways 1 Manually control via GPIOs 2 Associate one or more upper address pins to CE Bec...

Page 871: ...Description Value No effect 0 Invert EPI clock to ensure the rising edge is centered for outbound signal s setup and hold Inbound signal is captured on rising edge EPI clock 1 0 RW CLKINV 29 Input Re...

Page 872: ...W WRHIGH 21 READ Strobe Polarity Description Value The READ strobe for CS0n is RDn active Low 0 The READ strobe for CS0n is RD active High 1 0 RW RDHIGH 20 ALE Strobe Polarity Description Value The ad...

Page 873: ...ocks to wait while an external FIFO ready signal is holding off a transaction FFULL and FEMPTY When this field is clear the transaction can be held off forever without a system interrupt Note When the...

Page 874: ...Active RDn is 8 EPI clocks 0x3 This field is used in conjunction with the EPIBAUD register 0x0 RW RDWS 5 4 Software should not rely on the value of a reserved bit To provide compatibility with future...

Page 875: ...ription Value ADMUX AD 15 0 Data and Address are muxed 0x0 ADNONMUX D 15 0 Data and address are separate This mode is not practical in HB16 mode for normal peripherals because there are generally not...

Page 876: ...FO and or the WFIFO or by rate of accesses from software or DMA General custom interfaces of any speed The configuration allows for choice of an output clock free running or gated a framing signal wit...

Page 877: ...ME signal on each transaction A FRMCNT of 1 means the FRAME signal is inverted every other transaction a value of 15 means every sixteenth transaction If FRM50 is set the frame is held high for FRMCNT...

Page 878: ...size cannot be used with data sizes other than 8 0x3 0x0 RW ASIZE 5 4 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit...

Page 879: ...FG2 Base 0x400D 0000 Offset 0x014 Type RW reset 0x0008 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ALEHIGH RDHIGH WRHIGH reserved CSCFG CSBAUD CSCFGEXT reserved RO RO RO RW RW RW RO...

Page 880: ...xing is needed the WR signal EPI0S29 and the RD signal EPI0S28 can be used to latch the address when CSn is low 0x1 Dual CSn Configuration EPI0S30 is used as CS0n and EPI0S27 is used as CS1n Whether C...

Page 881: ...e polarity Description Value Same Baud Rate and Same Sub Mode All CSn use the baud rate for the external bus that is defined by the COUNT0 field in the EPIBAUD register and the sub mode programmed in...

Page 882: ...s determined by two methods If only external RAM or external PER is enabled in the address map the most significant address bit for a respective external address map controls CS0n or CS1n If both exte...

Page 883: ...ould be preserved across a read modify write operation 0 RO reserved 18 8 CS1n Write Wait States This field adds wait states to the data phase of CS1n accesses the address phase is not affected The ef...

Page 884: ...ve RDn is 8 EPI clocks 0x3 0x0 RW RDWS 5 4 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across...

Page 885: ...00D 0000 Offset 0x014 Type RW reset 0x0008 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 BURST RDCRE WRCRE ALEHIGH RDHIGH WRHIGH reserved CSCFG CSBAUD CSCFGEXT reserved RW RW RW RW RW RW RO RO...

Page 886: ...uxing is needed the WR signal EPI0S29 and the RD signal EPI0S28 can be used to latch the address when CSn is low 0x1 Dual CSn Configuration EPI0S30 is used as CS0n and EPI0S27 is used as CS1n Whether...

Page 887: ...polarity Description Value Same Baud Rate and Same Sub Mode All CSn use the baud rate for the external bus that is defined by the COUNT0 field in the EPIBAUD register and the sub mode programmed in t...

Page 888: ...ddress bit for a respective external address map This configuration can be used for a RAM bank split between 2 devices as well as when using both an external RAM and an external peripheral 0x2 ALE wit...

Page 889: ...RDCRE set the next access is a read of the PSRAM s Configuration Register CR This bit self clears once the CRE access is complete The address for the CRE access is located at EPIHBPSRAM 19 18 The rea...

Page 890: ...s field adds wait states to the data phase of CS1n accesses the address phase is not affected The effect is to delay the rising edge of RDn Oen or the falling edge of RD Each wait state encoding adds...

Page 891: ...configuration is for CS1n Note The CSBAUD bit must be set to enable this CS1n MODE field If CSBAUD is clear all chip selects use the MODE configuration defined in the EPIHB16CFG register Description V...

Page 892: ...n also be shared between the code space and memory or peripheral space If the ECADR field is 0x1 ERADR field is 0x0 and the EPADR field is not 0x0 then CS0n is asserted for the address range defined b...

Page 893: ...FF FFFF 0x2 256MB lower address range 0x000 0000 to 0x0FFF FFFF 0x3 0x0 RW ECSZ 11 10 External Code Address This field selects address mapping for the external code area Description Value Not mapped 0...

Page 894: ...size of the external memory is smaller it wraps upper address bits unused Description Value 256 bytes lower address range 0x00 to 0xFF 0x0 64 KB lower address range 0x0000 to 0xFFFF 0x1 16 MB lower a...

Page 895: ...ing this register while a read is active has an unpredictable effect EPI Read Size n EPIRSIZEn Base 0x400D 0000 Offset 0x020 Type RW reset 0x0000 0003 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r...

Page 896: ...tains the next address that would have been read had it not been cancelled For example if reading by bytes and 0x103 had been read but not 0x104 this register contains 0x104 In this manner the system...

Page 897: ...ite is performed through the address mapped area at 0x6000 0000 through 0xDFFF FFFF any current non blocking read is paused at the next safe boundary and the blocking request is inserted After complet...

Page 898: ...s responsibility to handle address wrap around Reading this register provides the current count A write of 0 cancels a non blocking read whether active now or pending Prior to writing a non zero valu...

Page 899: ...re should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x0000 00 RO reserv...

Page 900: ...usy Description Value The external interface is not performing a non blocking read 0 The external interface is performing a non blocking read or if the non blocking read is paused due to a write 1 0 R...

Page 901: ...O RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 COUNT reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0...

Page 902: ...that is at the top of the NBRFIFO and then empties that value from the NBRFIFO The alias registers can be used with the LDMIA instruction for more efficient operation for up to 8 registers See Cortex...

Page 903: ...the system such that after a read has been stalled due to any preceding writes in the WFIFO the error interrupt is generated Note that the excess stall is not prevented but an interrupt is generated a...

Page 904: ...gered until there are only two slots available Thus trigger is deasserted when there are two WRFIFO entries present This configuration is optimized for bursts of 2 0x2 Interrupt is triggered until the...

Page 905: ...pe RO reset 0x0000 0004 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12...

Page 906: ...RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TXCNT RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Rese...

Page 907: ...ly on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x000 RO reserved 31 5 Write uDMA I...

Page 908: ...ot masked and can trigger an interrupt to the interrupt controller 1 0 RW RDIM 1 Error Interrupt Mask Description Value ERRIS in the EPIRIS register is masked and does not cause an interrupt 0 ERRIS i...

Page 909: ...S WRRIS DMARDRIS DMAWRRIS reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the valu...

Page 910: ...is below the trigger point programmed by the RDFIFO field 0 RO RDRIS 1 Error Raw Interrupt Status The error interrupt occurs in the following situations WFIFO Full For a full WFIFO to generate an err...

Page 911: ...Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across...

Page 912: ...f valid entries in the NBRFIFO is below the range specified by the trigger level or the interrupt is masked 0 The number of valid entries in the NBRFIFO is within the range specified by the trigger le...

Page 913: ...0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TOUT RSTALL WTFULL DMARDIC DMAWRIC reserved RW1C RW1C RW1C W1C W1C RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset...

Page 914: ...dy signals hold a transaction for more than the count in the MAXWAIT field when not 0 Description Value No timeout error has occurred 0 A timeout error has occurred 1 Writing a 1 to this bit clears it...

Page 915: ...ad modify write operation 0x000 RO reserved 31 22 CS2n WRITE Strobe Polarity This field is used if the CSBAUD bit is enabled in EPIHB8CFG2 Description Value The WRITE strobe for CS2n accesses is WRn a...

Page 916: ...ield adds wait states to the data phase of CS2n accesses the address phase is not affected The effect is to delay the rising edge of RDn Oen or the falling edge of RD Each wait state adds 2 EPI clock...

Page 917: ...ion on how this bit field affects the operation of the EPI signals Note The CSBAUD bit must be set to enable this CS2n MODE field If CSBAUD is clear all chip selects use the MODE configuration defined...

Page 918: ...it To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x000 RO reserved 31 22 CS2n WRITE Strobe Polarity This field is u...

Page 919: ...dress for the CRE access is located at EPIHBPSRAM 19 18 The read data is returned on EPIHBPSRAM 15 0 Description Value No Action 0 Start CRE read transaction for CS2n 1 0 RW RDCRE 17 CS2n Burst Mode B...

Page 920: ...states to the data phase of CS2n accesses the address phase is not affected The effect is to delay the rising edge of RDn Oen or the falling edge of RD Each wait state adds 2 EPI clock cycles to the...

Page 921: ...als Note The CSBAUD bit must be set to enable this CS2n MODE field If CSBAUD is clear all chip selects use the MODE configuration defined in the EPIHB16CFG register Description Value ADMUX AD 15 0 Dat...

Page 922: ...d modify write operation 0x0 RO reserved 31 22 CS3n WRITE Strobe Polarity This field is used if the CSBAUD bit is enabled in EPIHB8CFG2 Description Value The WRITE strobe for CS3n accesses is WRn acti...

Page 923: ...ield adds wait states to the data phase of CS3n accesses the address phase is not affected The effect is to delay the rising edge of RDn Oen or the falling edge of RD Each wait state adds 2 EPI clock...

Page 924: ...tion on how this bit field affects the operation of the EPI signals Note The CSBAUD bit must be set to enable this CS3n MODE field If CSBAUD is clear all chip selects use the MODE configuration define...

Page 925: ...it To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x00 RO reserved 31 22 CS3n WRITE Strobe Polarity This field is us...

Page 926: ...he address for the CRE access is located at EPIHBPSRAM 19 18 The read data is returned on EPIHBPSRAM 15 0 Description Value No Action 0 Start CRE read transaction for CS3n 1 0 RW RDCRE 17 CS3n Burst M...

Page 927: ...eld adds wait states to the data phase of CS3n accesses the address phase is not affected The effect is to delay the rising edge of RDn Oen or the falling edge of RD Each wait state adds 2 EPI clock c...

Page 928: ...als Note The CSBAUD bit must be set to enable this CS3n MODE field If CSBAUD is clear all chip selects use the MODE configuration defined in the EPIHB16CFG register Description Value ADMUX AD 15 0 Dat...

Page 929: ...e operation 0x00 RO reserved 31 26 CS0n Input Ready Delay Description Value reserved 0 Stall begins one EPI clocks past iRDY low being sampled on the rising edge of EPIO clock 1 Stall begins two EPI c...

Page 930: ...t rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x0 RO reserved 3 1 Read Wait S...

Page 931: ...with future products the value of a reserved bit should be preserved across a read modify write operation 0x00 RO reserved 31 26 CS0n Input Ready Delay Description Value reserved 0 Stall begins one E...

Page 932: ...WRWS field in EPIHB16CFG This field is not applicable in BURST mode Description Value No change in the number of wait state clock cycles programmed in the in WRWS field in EPIHB16CFG register 0 Wait s...

Page 933: ...te operation 0x00 RO reserved 31 26 CS1n Input Ready Delay Description Value reserved 0 Stall begins one EPI clocks past iRDY low being sampled on the rising edge of EPIO clock 1 Stall begins two EPI...

Page 934: ...t rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x0 RO reserved 3 1 CS1n Read W...

Page 935: ...ty with future products the value of a reserved bit should be preserved across a read modify write operation 0x00 RO reserved 31 26 CS1n Input Ready Delay Description Value reserved 0 Stall begins one...

Page 936: ...WS field in EPIHB16CFG2 This field is not applicable in BURST mode Description Value No change in the number of wait state clock cycles programmed in the in WRWS field in EPIHB16CFG2 register 0 Wait s...

Page 937: ...te operation 0x00 RO reserved 31 26 CS2n Input Ready Delay Description Value reserved 0 Stall begins one EPI clocks past iRDY low being sampled on the rising edge of EPIO clock 1 Stall begins two EPI...

Page 938: ...t rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x0 RO reserved 3 1 CS2n Read W...

Page 939: ...ty with future products the value of a reserved bit should be preserved across a read modify write operation 0x00 RO reserved 31 26 CS2n Input Ready Delay Description Value reserved 0 Stall begins one...

Page 940: ...WS field in EPIHB16CFG3 This field is not applicable in BURST mode Description Value No change in the number of wait state clock cycles programmed in the in WRWS field in EPIHB16CFG3 register 0 Wait s...

Page 941: ...modify write operation 0x00 RO reserved 31 26 CS3n Input Ready Delay Description Value reserved 0 Stall begins one EPI clocks past iRDY low being sampled on the rising edge of EPIO clock 1 Stall begin...

Page 942: ...Wait state value is now WRWS 1 WRWS field is programmed in EPIHB8CFG4 1 0 RW WRWSM 4 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of...

Page 943: ...ty with future products the value of a reserved bit should be preserved across a read modify write operation 0x00 RO reserved 31 26 CS3n Input Ready Delay Description Value reserved 0 Stall begins one...

Page 944: ...WS field in EPIHB16CFG4 This field is not applicable in BURST mode Description Value No change in the number of wait state clock cycles programmed in the in WRWS field in EPIHB16CFG4 register 0 Wait s...

Page 945: ...RW RW RW RW RW RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CR RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 0 0 0 0 0 0 0 0...

Page 946: ...e contains all of the control registers to which the input context interfaces Because CRC calculations are a single cycle as soon as data is written to CRC Data Input CRCDIN register the result of CRC...

Page 947: ...he ENDIAN field in the CRCCTRL register Swap byte in half word Swap half word Input data width is four bytes hence the configuration only affects the four byte word The ENDIAN bit field supports the f...

Page 948: ...offset 0x410 4 Repeatedly write the DATAIN field in the CRC Data Input CRCDIN register offset 0x414 If the SIZE bit in the CRCCTRL register is set to select byte the CRC engine operates in byte mode a...

Page 949: ...me Offset 950 CRC Control 0x0000 0000 RW CRCCTRL 0x400 952 CRC SEED Context 0x0000 0000 RW CRCSEED 0x410 953 CRC Data Input 0x0000 0000 RW CRCDIN 0x414 954 CRC Post Processing Result 0x0000 0000 RO CR...

Page 950: ...ify write operation 0x0000 RO reserved 31 15 CRC Initialization Determines initialization value of CRC This field is self clearing With the first write to the CRC Data Input CRCDIN register this value...

Page 951: ...0 RO reserved 6 Endian Control This field is used to program the endian configuration The encodings below are with respect to an input word B3 B2 B1 B0 Refer to Table 12 1 on page 947 for more inform...

Page 952: ...4403 0000 Offset 0x410 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SEED RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3...

Page 953: ...DATAIN RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DATAIN RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 0 0...

Page 954: ...26 27 28 29 30 31 RSLTPP RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RSLTPP RO RO RO RO RO RO RO RO RO RO RO RO RO...

Page 955: ...neral Purpose Timer Module GPTM contains eight 16 32 bit GPTM blocks with the following functional options Operating modes 16 or 32 bit programmable one shot timer 16 or 32 bit programmable periodic t...

Page 956: ...PTMTBILR GPTMTBMR GPTMTAPS Timer A Control GPTMTAPMR GPTMTAPR GPTMTAMATCHR GPTMTAILR GPTMTAMR GPTMTAV GPTMTAR TA Comparator Timer A Timer B GPTMTBV GPTMTBR TB Comparator GPTMRTCPD RTC Control Timer A...

Page 957: ...ed into the PMCn field in the GPIO Port Control GPIOPCTL register page 787 to assign the GP Timer signal to the specified GPIO port pin For more information on configuring GPIOs see General Purpose In...

Page 958: ...e shown in Table 13 3 on page 958 Note that when counting down in one shot or periodic modes the prescaler acts as a true prescaler and contains the least significant bits of the count When counting u...

Page 959: ...k Configuration ALTCLKCFG register offset 0x138 in the System Control Module The alternate clock source options available are PIOSC RTCOSC and LFIOSC Refer to System Control on page 220 for additional...

Page 960: ...eloads with 0x0 If configured to be a one shot timer the timer stops counting and clears the TnEN bit in the GPTMCTL register If configured as a periodic timer the timer starts counting again on the n...

Page 961: ...e TnSTALL bit in the GPTMCTL register is set and the RTCEN bit is not set in the GPTMCTL register the timer freezes counting while the processor is halted by the debugger The timer resumes counting wh...

Page 962: ...he GPTMCTL register the counter starts counting up from its preloaded value of 0x1 When the current count value matches the preloaded value in the GPTMTnMATCHR registers the GPTM asserts the RTCRIS bi...

Page 963: ...t Status GPTMMIS register In up count mode the current count of the input events is held in both the GPTMTnR and GPTMTnV registers In down count mode the current count of the input events can be obtai...

Page 964: ...ge Time mode by setting the TnCMR bit in the GPTMTnMR register and the type of event that the timer captures is determined by the TnEVENT fields of the GPTMCTL register Table 13 8 on page 964 shows th...

Page 965: ...configured to capture rising edge events Each time a rising edge event is detected the current count value is loaded into the GPTMTnR and GPTMTnPS registers and is held there until another rising edge...

Page 966: ...he GPTM Raw Interrupt Status GPTMRIS register and holds it until it is cleared by writing the GPTM Interrupt Clear GPTMICR register If the capture mode event interrupt is enabled in the GPTM Interrupt...

Page 967: ...hen the TnPLO and TnMRSU bits are set and the GPTMTnMATCHR value is greater than the GPTMTnILR value Figure 13 5 CCP Output GPTMTnMATCHR GPTMTnILR CCP CounterValue GPTMnMATCHR GPTMnILR CCP set if GPTM...

Page 968: ...the TnWOT bit in the GPTMTnMR register When the TnWOT bit is set Timer N 1 does not begin counting until the timer in the previous position in the daisy chain Timer N reaches its time out event The da...

Page 969: ...egister Note All timers must use the same clock source for this feature to work correctly Table 13 10 on page 969 shows the actions for the timeout event performed when the timers are synchronized in...

Page 970: ...gether to create a single dma_req pulse that is sent to the DMA When the DMA transfer has completed a dma_done signal is sent to the timer resulting in a DMAnRIS bit set in the GPTMRIS register 13 3 7...

Page 971: ...nce 1 Ensure the timer is disabled the TnEN bit in the GPTMCTL register is cleared before making any changes 2 Write the GPTM Configuration Register GPTMCFG with a value of 0x0000 0000 3 Configure the...

Page 972: ...bit in the GPTMRIS register and continues counting until Timer A is disabled or a hardware reset The interrupt is cleared by writing the RTCCINT bit in the GPTMICR register Note that if the GPTMTnILR...

Page 973: ...write the prescale value to the GPTM Timer n Prescale Register GPTMTnPR 6 Load the timer start value into the GPTM Timer n Interval Load GPTMTnILR register 7 If interrupts are required set the CnEIM b...

Page 974: ...d the change takes effect at the next cycle after the write 13 5 Register Map Table 13 11 on page 974 lists the GPTM registers The offset listed is a hexadecimal increment to the register s address re...

Page 975: ...1 GPTM TimerB Prescale Match 0x0000 0000 RW GPTMTBPMR 0x044 1012 GPTM Timer A 0xFFFF FFFF RO GPTMTAR 0x048 1013 GPTM Timer B 0x0000 FFFF RO GPTMTBR 0x04C 1014 GPTM Timer A Value 0xFFFF FFFF RW GPTMTAV...

Page 976: ...RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 GPTMCFG reserved RW RW RW RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Descr...

Page 977: ...0E 1000 Offset 0x004 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2...

Page 978: ...MATCHR register and the GPTMTAPR register if used on the next cycle 0 Update the GPTMTAMATCHR register and the GPTMTAPR register if used on the next timeout 1 If the timer is disabled TAEN is clear wh...

Page 979: ...LD 8 GPTM Timer A Snap Shot Mode Description Value Snap shot mode is disabled 0 If Timer A is configured in the periodic mode the actual free running capture or snapshot value of Timer A is loaded at...

Page 980: ...d periodic modes 1 0 RW TAMIE 5 GPTM Timer A Count Direction Description Value The timer counts down 0 The timer counts up When counting up the timer starts from a value of 0x0 1 When in PWM or RTC mo...

Page 981: ...Description Value Reserved 0x0 One Shot Timer mode 0x1 Periodic Timer mode 0x2 Capture mode 0x3 The Timer mode is based on the timer configuration defined by bits 2 0 in the GPTMCFG register 0x0 RW T...

Page 982: ...1000 Offset 0x008 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3...

Page 983: ...PTMTBMATCHR register and the GPTMTBPR register if used on the next cycle 0 Update the GPTMTBMATCHR register and the GPTMTBPR register if used on the next timeout 1 If the timer is disabled TBEN is cle...

Page 984: ...e out event into the GPTM Timer B GPTMTBR register If the timer prescaler is used the prescaler snapshot is loaded into the GPTM Timer B GPTMTBPR 1 0 RW TBSNAPS 7 GPTM Timer B Wait on Trigger Descript...

Page 985: ...is enabled 0 PWM mode is enabled 1 Note To enable PWM mode you must also clear the TBCMR bit and configure the TBMR field to 0x1 or 0x2 0 RW TBAMS 3 GPTM Timer B Capture Mode The TBCMR values are def...

Page 986: ...PWML reserved TBEN TBSTALL TBEVENT reserved TBOTE TBPWML reserved RW RW RW RW RW RW RW RO RW RW RW RW RO RW RW RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Softw...

Page 987: ...or is halted by the debugger 0 Timer B freezes counting while the processor is halted by the debugger 1 If the processor is executing normally the TBSTALL bit is ignored 0 RW TBSTALL 9 GPTM Timer B En...

Page 988: ...nSTALL is set 0 RW RTCEN 4 GPTM Timer A Event Mode The TAEVENT values are defined as follows Description Value Positive edge 0x0 Negative edge 0x1 Reserved 0x2 Both edges 0x3 Note If PWM output invers...

Page 989: ...lues are defined as follows Description Value Timer A is disabled 0 Timer A is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register 1 0 RW TAEN 0 989 June 18 2014...

Page 990: ...SYNCT7 WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provi...

Page 991: ...affected 0x0 A timeout event for Timer A of GPTM3 is triggered 0x1 A timeout event for Timer B of GPTM3 is triggered 0x2 A timeout event for both Timer A and Timer B of GPTM3 is triggered 0x3 0x0 WO S...

Page 992: ...not affected 0x0 A timeout event for Timer A of GPTM0 is triggered 0x1 A timeout event for Timer B of GPTM0 is triggered 0x2 A timeout event for both Timer A and Timer B of GPTM0 is triggered 0x3 0x0...

Page 993: ...RW RO RW RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products t...

Page 994: ...ify write operation 0 RO reserved 7 6 GPTM Timer A DMA Done Interrupt Mask The DMAAIM values are defined as follows Description Value Interrupt is disabled 0 Interrupt is enabled 1 0 RW DMAAIM 5 GPTM...

Page 995: ...s Description Value Interrupt is disabled 0 Interrupt is enabled 1 0 RW CAMIM 1 GPTM Timer A Time Out Interrupt Mask The TATOIM values are defined as follows Description Value Interrupt is disabled 0...

Page 996: ...03 4000 16 32 bit Timer 5 base 0x4003 5000 16 32 bit Timer 6 base 0x400E 0000 16 32 bit Timer 7 base 0x400E 1000 Offset 0x01C Type RO reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31...

Page 997: ...s occurred for Timer B This interrupt asserts when the values in the GPTMTBR and GPTMTBPR match the values in the GPTMTBMATCHR and GPTMTBPMR when configured in Input Edge Time mode 1 This bit is clear...

Page 998: ...he subtimer is configured in Input Edge Time mode 1 This bit is cleared by writing a 1 to the CAECINT bit in the GPTMICR register 0 RO CAERIS 2 GPTM Timer A Capture Mode Match Raw Interrupt Descriptio...

Page 999: ...DMABMIS reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved b...

Page 1000: ...ut interrupt has occurred 1 This bit is cleared by writing a 1 to the TBTOCINT bit in the GPTMICR register 0 RO TBTOMIS 8 Software should not rely on the value of a reserved bit To provide compatibili...

Page 1001: ...1 to the CAECINT bit in the GPTMICR register 0 RO CAEMIS 2 GPTM Timer A Capture Mode Match Masked Interrupt Description Value A Capture A Mode Match interrupt has not occurred or is masked 0 An unmask...

Page 1002: ...write operation 0x0000 RO reserved 31 14 GPTM Timer B DMA Done Interrupt Clear Writing a 1 to this bit clears the DMABRIS bit in the GPTMRIS register and the DMABMIS bit in the GPTMMIS register 0 W1C...

Page 1003: ...nd the RTCMIS bit in the GPTMMIS register 0 W1C RTCCINT 3 GPTM Timer A Capture Mode Event Interrupt Clear Writing a 1 to this bit clears the CAERIS bit in the GPTMRIS register and the CAEMIS bit in th...

Page 1004: ...bit Timer 1 base 0x4003 1000 16 32 bit Timer 2 base 0x4003 2000 16 32 bit Timer 3 base 0x4003 3000 16 32 bit Timer 4 base 0x4003 4000 16 32 bit Timer 5 base 0x4003 5000 16 32 bit Timer 6 base 0x400E 0...

Page 1005: ...er 2 base 0x4003 2000 16 32 bit Timer 3 base 0x4003 3000 16 32 bit Timer 4 base 0x4003 4000 16 32 bit Timer 5 base 0x4003 5000 16 32 bit Timer 6 base 0x400E 0000 16 32 bit Timer 7 base 0x400E 1000 Off...

Page 1006: ...Timer B Match GPTMTBMATCHR register In a 16 bit mode the upper 16 bits of this register read as 0s and have no effect on the state of GPTMTBMATCHR GPTM Timer A Match GPTMTAMATCHR 16 32 bit Timer 0 ba...

Page 1007: ...return the current match value of Timer B and writes are ignored In a 16 bit mode bits 15 0 are used for the match value Bits 31 16 are reserved in both cases GPTM Timer B Match GPTMTBMATCHR 16 32 bit...

Page 1008: ...x4003 5000 16 32 bit Timer 6 base 0x400E 0000 16 32 bit Timer 7 base 0x400E 1000 Offset 0x038 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO...

Page 1009: ...5000 16 32 bit Timer 6 base 0x400E 0000 16 32 bit Timer 7 base 0x400E 1000 Offset 0x03C Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO...

Page 1010: ...23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TAPSMR reserved RW RW RW RW RW RW...

Page 1011: ...et 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15...

Page 1012: ...e prescalar in periodic snapshot mode read the Timer A Prescale Snapshot GPTMTAPS register GPTM Timer A GPTMTAR 16 32 bit Timer 0 base 0x4003 0000 16 32 bit Timer 1 base 0x4003 1000 16 32 bit Timer 2...

Page 1013: ...ead the value of the prescalar in periodic snapshot mode read the Timer B Prescale Snapshot GPTMTBPS register GPTM Timer B GPTMTBR 16 32 bit Timer 0 base 0x4003 0000 16 32 bit Timer 1 base 0x4003 1000...

Page 1014: ...rescaler meaning bits 23 16 count down before decrementing the value in bits 15 0 The prescaler in bits 31 24 always reads as 0 GPTM Timer A Value GPTMTAV 16 32 bit Timer 0 base 0x4003 0000 16 32 bit...

Page 1015: ...ng bits 23 16 count down before decrementing the value in bits 15 0 The prescaler in bits 31 24 always reads as 0 GPTM Timer B Value GPTMTBV 16 32 bit Timer 0 base 0x4003 0000 16 32 bit Timer 1 base 0...

Page 1016: ...mer 7 base 0x400E 1000 Offset 0x058 Type RO reset 0x0000 7FFF 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 1017: ...00 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PSS RO RO R...

Page 1018: ...x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PSS...

Page 1019: ...eset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify writ...

Page 1020: ...ger is enabled 1 0 RW TAMDMAEN 4 GPTM A RTC Match Event DMA Trigger Enable When this bit is enabled a Timer A dma_req signal is sent to the DMA when a RTC match has occurred Description Value Timer A...

Page 1021: ...s bit is enabled a Timer A dma_req signal is sent to the DMA on a time out event Description Value Timer A Time Out DMA trigger is disabled 0 Timer A Time Out DMA trigger is enabled 1 0 RW TATODMAEN 0...

Page 1022: ...eset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across...

Page 1023: ...ger is enabled 1 0 RW TAMADCEN 4 GPTM RTC Match Event ADC Trigger Enable When this bit is enabled a trigger signal is sent to the ADC when a RTC match has occurred Description Value Timer A RTC Match...

Page 1024: ...this bit is enabled a trigger signal is sent to the ADC on a time out event Description Value Timer A Time Out Event ADC trigger is disabled 0 Timer A Time Out Event ADC trigger is enabled 1 0 RW TAT...

Page 1025: ...n Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify w...

Page 1026: ...on Value Timer A and Timer B counters are 16 bits each with an 8 bit prescale counter 0 Timer A and Timer B counters are 32 bits each with a 16 bit prescale counter 1 0x0 RO SIZE 3 0 June 18 2014 1026...

Page 1027: ...0x4003 1000 16 32 bit Timer 2 base 0x4003 2000 16 32 bit Timer 3 base 0x4003 3000 16 32 bit Timer 4 base 0x4003 4000 16 32 bit Timer 5 base 0x4003 5000 16 32 bit Timer 6 base 0x400E 0000 16 32 bit Tim...

Page 1028: ...TCTL register to indicate when a write to a WDT1 register is complete Software can use this bit to ensure that the previous access has completed before starting the next access The TM4C1294NCPDT contr...

Page 1029: ...bit counter is re loaded with the value of the Watchdog Timer Load WDTLOAD register and the timer resumes counting down from that value Once the Watchdog Timer has been configured the Watchdog Timer...

Page 1030: ...Configuration To use the WDT its peripheral clock must be enabled by setting the Rn bit in the Watchdog Timer Run Mode Clock Gating Control RCGCWD register see page 379 The Watchdog Timer is configure...

Page 1031: ...5 0xFD4 1043 Watchdog Peripheral Identification 6 0x0000 0000 RO WDTPeriphID6 0xFD8 1044 Watchdog Peripheral Identification 7 0x0000 0000 RO WDTPeriphID7 0xFDC 1045 Watchdog Peripheral Identification...

Page 1032: ...Load WDTLOAD WDT0 base 0x4000 0000 WDT1 base 0x4000 1000 Offset 0x000 Type RW reset 0xFFFF FFFF 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 WDTLOAD RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW...

Page 1033: ...9 30 31 WDTVALUE RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 WDTVALUE RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO...

Page 1034: ...oftware that another write or read may be started safely Software should poll WDTCTL for WRC 1 prior to accessing another register Note that WDT0 does not have this restriction as it runs off the syst...

Page 1035: ...tput Setting this bit enables the Watchdog Timer 1 0 RW RESEN 1 Watchdog Interrupt Enable The INTEN values are defined as follows Description Value Interrupt event disabled Once this bit is set it can...

Page 1036: ...er The WDTICR register should only be written when interrupts have triggered and need to be serviced Watchdog Interrupt Clear WDTICR WDT0 base 0x4000 0000 WDT1 base 0x4000 1000 Offset 0x00C Type WO re...

Page 1037: ...0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 WDTRIS reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Nam...

Page 1038: ...0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 WDTMIS reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software...

Page 1039: ...re should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x0000 00 RO reserv...

Page 1040: ...e RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 WDTLOCK RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 1...

Page 1041: ...RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PID4 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 1042: ...RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PID5 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0...

Page 1043: ...RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PID6 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 1044: ...RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PID7 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0...

Page 1045: ...RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PID0 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 R...

Page 1046: ...RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PID1 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 1 1 0 0 0 0 0 0 0...

Page 1047: ...RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PID2 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 Re...

Page 1048: ...RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PID3 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 0 0 0 0 0 0 0 0 0 0 0...

Page 1049: ...O RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CID0 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 Res...

Page 1050: ...O RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CID1 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 1 1 1 1 0 0 0 0 0...

Page 1051: ...RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CID2 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Rese...

Page 1052: ...O RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CID3 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 0 0 0 1 1 0 1 0 0 0 0 0...

Page 1053: ...e trigger source for ADC0 and ADC1 may be independent or the two ADC modules may operate from the same trigger source and operate on the same or different inputs A phase shifter can delay the start of...

Page 1054: ...nverter modules These two modules ADC0 and ADC1 share the same 20 analog input channels Each ADC module operates independently and can therefore execute different sample sequences sample any of the an...

Page 1055: ...are analog functions for some GPIO signals The column in the table below titled Pin Mux Pin Assignment lists the GPIO pin placement for the ADC signals These signals are configured by clearing the cor...

Page 1056: ...using a programmable sequence based approach instead of the traditional single or double sampling approaches found on many ADC modules Each sample sequence is a fully programmed series of consecutive...

Page 1057: ...an be set in the nibble associated with the fifth sample allowing Sequencer 0 to complete execution of the sample sequence after the fifth sample After a sample sequence completes execution the result...

Page 1058: ...they are prioritized for processing by the values in the ADC Sample Sequencer Priority ADCSSPRI register Valid priority values are in the range of 0 3 with 0 being the highest priority and 3 being the...

Page 1059: ...n the ADC resolution in a single sampling interval The input circuitry includes the external source resistance as well as the input resistance and capacitance of the ADC RADC and CADC The values for R...

Page 1060: ...ple with a phase lag PHASE is nonzero For a sample rate of two million samples second at 16MHz the TSHn field of all of the sequencer samples of both ADCs must be programmed to 0x0 and the PHASE field...

Page 1061: ...s not required that the TSHn fields be the same in a skewed sample If an application has varying analog input resistance then TSHn and PHASE may vary according to operational requirements Figure 15 5...

Page 1062: ...ital Converter Run Mode Clock Gating Control RCGCADC register 15 3 3 Hardware Sample Averaging Circuit Higher precision results can be generated using the hardware averaging circuit however the improv...

Page 1063: ...power high precision conversion value The successive approximation uses a switched capacitor array to perform the dual functions of sampling and holding the signal as well as providing the 12 bit DAC...

Page 1064: ...ut paths to minimize the distortion and cross talk on the inputs Detailed information on the ADC power supplies and analog inputs can be found in Analog to Digital Converter ADC on page 1861 15 3 4 1...

Page 1065: ...t be taken to supply a reference voltage of acceptable quality Figure 15 9 on page 1065 shows the ADC conversion function of the analog inputs Figure 15 9 ADC Conversion Result 0xFFF VIN 0xC00 0x800 0...

Page 1066: ...0x800 If VIND 0 then the conversion result 0x800 range is 0x800 0xFFF If VIND 0 then the conversion result 0x800 range is 0 0x800 When using differential sampling the following definitions are relevan...

Page 1067: ...EFP VREFN V 0xFFF 0x800 Input Saturation VREFP VREFN 15 3 6 Internal Temperature Sensor The temperature sensor serves two primary purposes 1 to notify the system that internal temperature is too high...

Page 1068: ...om the ADC that are sent to the digital comparators are compared against the user programmable limits in the ADC Digital Comparator Range ADCDCCMPn registers The ADC can be configured to generate an i...

Page 1069: ...of conditions is met the corresponding digital comparator trigger to the PWM module is asserted 15 3 7 2 Operational Modes Four operational modes are provided to support a broad range of applications...

Page 1070: ...he same value effectively creating two regions but COMP1 must always be greater than or equal to the value of COMP0 A COMP1 value that is less than COMP0 generates unpredictable results Low Band Opera...

Page 1071: ...3 Mid Band Operation CIC 0x1 and or CTC 0x1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 0 1 1 1 0 0 0 0 0 Always Once Hysteresis Always Hysteresis Once COMP0 COMP1 High Band Operation To operate in...

Page 1072: ...priate GPIO modules via the RCGCGPIO register see page 382 To find out which GPIO ports to enable refer to Signal Description on page 1055 3 Set the GPIO AFSEL bits for the ADC input pins see page 770...

Page 1073: ...nding nibble in the ADCSSCTLn register When programming the last nibble ensure that the END bit is set Failure to set the END bit causes unpredictable behavior 6 If interrupts are to be used set the c...

Page 1074: ...Multiplexer Select 0 0x0000 0000 RW ADCSSEMUX0 0x058 1127 ADC Sample Sequence 0 Sample and Hold Time 0x0000 0000 RW ADCSSTSH0 0x05C 1129 ADC Sample Sequence Input Multiplexer Select 1 0x0000 0000 RW...

Page 1075: ...1 0x0000 0000 RW ADCDCCTL1 0xE04 1153 ADC Digital Comparator Control 2 0x0000 0000 RW ADCDCCTL2 0xE08 1153 ADC Digital Comparator Control 3 0x0000 0000 RW ADCDCCTL3 0xE0C 1153 ADC Digital Comparator C...

Page 1076: ...ister Descriptions The remainder of this section lists and describes the ADC registers in numerical order by address offset June 18 2014 1076 Texas Instruments Production Data Analog to Digital Conver...

Page 1077: ...cts the value of a reserved bit should be preserved across a read modify write operation 0 RO reserved 31 17 ADC Busy Description Value ADC is idle 0 ADC is busy 1 Note In order to use the BUSY bit th...

Page 1078: ...reserved bit should be preserved across a read modify write operation 0 RO reserved 7 4 ADC SS3 Enable Description Value Sample Sequencer 3 is disabled 0 Sample Sequencer 3 is enabled 1 0 RW ASEN3 3...

Page 1079: ...value of a reserved bit should be preserved across a read modify write operation 0x000 RO reserved 31 17 Digital Comparator Raw Interrupt Status Description Value All bits in the ADCDCISC register ar...

Page 1080: ...ved 7 4 SS3 Raw Interrupt Status Description Value An interrupt has not occurred 0 A sample has completed conversion and the respective ADCSSCTL3 IEn bit is set enabling a raw interrupt 1 This bit is...

Page 1081: ...as not occurred 0 A sample has completed conversion and the respective ADCSSCTL0 IEn bit is set enabling a raw interrupt 1 This bit is cleared by writing a 1 to the IN0 bit in the ADCISC register 0 RO...

Page 1082: ...000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 DCONSS0 DCONSS1 DCONSS2 DCONSS3 reserved RW RW RW RW RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7...

Page 1083: ...of a reserved bit should be preserved across a read modify write operation 0 RO reserved 15 12 SS3 DMA Interrupt Mask Description Value The status of Sample Sequencer 3 DMA does not affect the SS3 in...

Page 1084: ...register INR3 bit is sent to the interrupt controller 1 0 RW MASK3 3 SS2 Interrupt Mask Description Value The status of Sample Sequencer 2 does not affect the SS2 interrupt status 0 The raw interrupt...

Page 1085: ...IN2 IN3 reserved DMAIN0 DMAIN1 DMAIN2 DMAIN3 reserved RW1C RW1C RW1C RW1C RO RO RO RO RW1C RW1C RW1C RW1C RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field...

Page 1086: ...t rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 RO reserved 15 12 SS3 DMA Int...

Page 1087: ...ould not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 RO reserved 7 4 SS3 In...

Page 1088: ...earing this bit also clears the INR1 bit in the ADCRIS register 0 RW1C IN1 1 SS0 Interrupt Status and Clear Description Value No interrupt has occurred or the interrupt is masked 0 Both the INR0 bit i...

Page 1089: ...uld be preserved across a read modify write operation 0x0000 000 RO reserved 31 4 SS3 FIFO Overflow Description Value The FIFO has not overflowed 0 The FIFO for Sample Sequencer 3 has hit an overflow...

Page 1090: ...IFO for Sample Sequencer 0 has hit an overflow condition meaning that the FIFO is full and a write was requested When an overflow is detected the most recent write is dropped 1 This bit is cleared by...

Page 1091: ...1 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 EM0 EM1 EM2 EM3 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW...

Page 1092: ...e GPIO interrupt for the corresponding GPIO see ADC Trigger Source on page 750 0x4 Timer In addition the trigger must be enabled with the TnOTE bit in the GPTMCTL register page 986 0x5 PWM generator 0...

Page 1093: ...GPIO interrupt for the corresponding GPIO see ADC Trigger Source on page 750 0x4 Timer In addition the trigger must be enabled with the TnOTE bit in the GPTMCTL register page 986 0x5 PWM generator 0...

Page 1094: ...he GPIO interrupt for the corresponding GPIO see ADC Trigger Source on page 750 0x4 Timer In addition the trigger must be enabled with the TnOTE bit in the GPTMCTL register page 986 0x5 PWM generator...

Page 1095: ...GPIO interrupt for the corresponding GPIO see ADC Trigger Source on page 750 0x4 Timer In addition the trigger must be enabled with the TnOTE bit in the GPTMCTL register page 986 0x5 PWM generator 0...

Page 1096: ...ure products the value of a reserved bit should be preserved across a read modify write operation 0x0000 000 RO reserved 31 4 SS3 FIFO Underflow The valid configurations for this field are shown below...

Page 1097: ...escription Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read...

Page 1098: ...should be preserved across a read modify write operation 0x0 RO reserved 11 6 Generator 0 PWM Module Trigger Select This field selects in which PWM module the Generator 0 trigger is located Descripti...

Page 1099: ...ust be uniquely mapped The ADC may not operate properly if two or more fields are equal 0x3 RW SS3 13 12 Software should not rely on the value of a reserved bit To provide compatibility with future pr...

Page 1100: ...ty encoding of Sample Sequencer 0 A priority encoding of 0x0 is highest and 0x3 is lowest The priorities assigned to the sequencers must be uniquely mapped The ADC may not operate properly if two or m...

Page 1101: ...consistent phase lag the TSHn field in the ADCSSTSHn register must be the same for all sample steps of an ADC and for both ADC Modules The desired lag can be calculated by adding the sample and hold t...

Page 1102: ...ration 0x0000 000 RO reserved 31 4 Phase Lag This field selects the sample phase lag from the standard sample time Description Value The ADC samples are concurrent 0x0 The ADC sample lags by 1 ADC clo...

Page 1103: ...YNCWAIT reserved GSYNC RO RO RO RO RO RO RO RO RO RO RO RW RO RO RO RW Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SS0 SS1 SS2 SS3 reserved WO WO WO WO RO RO RO RO...

Page 1104: ...oftware is valid a read of this register returns no meaningful data WO SS2 2 SS1 Initiate Description Value No effect 0 Begin sampling on Sample Sequencer 1 if the sequencer is enabled in the ADCACTSS...

Page 1105: ...et 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 AVG reserved RW RW RW RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should n...

Page 1106: ...0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserve...

Page 1107: ...tor 2 Interrupt Status and Clear Description Value No interrupt 0 Digital Comparator 2 has generated an interrupt 1 This bit is cleared by writing a 1 0 RW1C DCINT2 2 Digital Comparator 1 Interrupt St...

Page 1108: ...O RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VREF reserved RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Des...

Page 1109: ...t Field 8th Sample Input Select The MUX7 field is used during the eighth sample of a sequence executed with the sample sequencer It specifies which of the analog inputs is sampled for the analog to di...

Page 1110: ...analog inputs is sampled for the analog to digital conversion 0x0 RW MUX2 11 8 2nd Sample Input Select The MUX1 field is used during the second sample of a sequence executed with the sample sequencer...

Page 1111: ...e Name Bit Field 8th Sample Temp Sensor Select Description Value The input pin specified by the ADCSSMUXn register is read during the eighth sample of the sample sequence 0 The temperature sensor is r...

Page 1112: ...If the MASK0 bit in the ADCIM register is set the interrupt is promoted to the interrupt controller 1 It is legal to have multiple samples within a sequence generate interrupts 0 RW IE6 26 7th Sample...

Page 1113: ...ample of the sequence 1 It is possible to end the sequence on any sample position Software must set an ENDn bit somewhere within the sequence Samples defined after the sample containing a set ENDn bit...

Page 1114: ...lect Description Value The analog inputs are not differentially sampled 0 The analog input is differentially sampled The corresponding ADCSSMUXn nibble must be set to the pair number i where the paire...

Page 1115: ...The input pin specified by the ADCSSMUXn register is read during the third sample of the sample sequence 0 The temperature sensor is read during the third sample of the sample sequence 1 0 RW TS2 11 3...

Page 1116: ...f the MASK0 bit in the ADCIM register is set the interrupt is promoted to the interrupt controller 1 It is legal to have multiple samples within a sequence generate interrupts 0 RW IE1 6 2nd Sample is...

Page 1117: ...le is End of Sequence Description Value Another sample in the sequence is the final sample 0 The first sample is the last sample of the sequence 1 It is possible to end the sequence on any sample posi...

Page 1118: ...FO is empty If the FIFO is not properly handled by software overflow and underflow conditions are registered in the ADCOSTAT and ADCUSTAT registers ADC Sample Sequence Result FIFO n ADCSSFIFOn ADC0 ba...

Page 1119: ...16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TPTR HPTR EMP...

Page 1120: ...x0 0x7 for FIFO0 0x0 0x3 for FIFO1 and FIFO2 and 0x0 for FIFO3 0x0 RO HPTR 7 4 FIFO Tail Pointer This field contains the current tail pointer index for the FIFO that is the next entry to be read Valid...

Page 1121: ...ecified by the S7DCSEL bit in the ADCSSDC0 register and the value is not written to the FIFO 1 0 RW S7DCOP 28 Software should not rely on the value of a reserved bit To provide compatibility with futu...

Page 1122: ...on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x0 RO reserved 7 5 Sample 1 Digital C...

Page 1123: ...sample from Sample Sequencer 0 Note Values not listed are reserved Description Value Digital Comparator Unit 0 ADCDCCMP0 and ADCDCCTL0 0x0 Digital Comparator Unit 1 ADCDCCMP1 and ADCDCCTL1 0x1 Digital...

Page 1124: ...CSEL 11 8 Sample 1 Digital Comparator Select This field has the same encodings as S7DCSEL but is used during the second sample 0x0 RW S1DCSEL 7 4 Sample 0 Digital Comparator Select This field has the...

Page 1125: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserve...

Page 1126: ...y on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x0 RO reserved 11 9 3rd Sample Inpu...

Page 1127: ...0 Sample and Hold Time ADCSSTSH0 ADC0 base 0x4003 8000 ADC1 base 0x4003 9000 Offset 0x05C Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 TSH4 TSH5 TSH6 TSH7 RW RW RW RW RW...

Page 1128: ...ourth sample of a sequence executed with the sample sequencer 0x0 RW TSH3 15 12 3rd Sample and Hold Period Select The TSH2 field is used during the third sample of a sequence executed with the sample...

Page 1129: ...crocontroller Configuring MUXn to be 0xC 0xF when the corresponding EMUXn bit is set results in undefined behavior ADC Sample Sequence Input Multiplexer Select n ADCSSMUXn ADC0 base 0x4003 8000 ADC1 b...

Page 1130: ...6 7 8 9 10 11 12 13 14 15 D0 END0 IE0 TS0 D1 END1 IE1 TS1 D2 END2 IE2 TS2 D3 END3 IE3 TS3 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset...

Page 1131: ...The input pin specified by the ADCSSMUXn register is read during the third sample of the sample sequence 0 The temperature sensor is read during the third sample of the sample sequence 1 0 RW TS2 11 3...

Page 1132: ...f the MASK0 bit in the ADCIM register is set the interrupt is promoted to the interrupt controller 1 It is legal to have multiple samples within a sequence generate interrupts 0 RW IE1 6 2nd Sample is...

Page 1133: ...le is End of Sequence Description Value Another sample in the sequence is the final sample 0 The first sample is the last sample of the sequence 1 It is possible to end the sequence on any sample posi...

Page 1134: ...Sample 3 Digital Comparator Operation Description Value The fourth sample is saved in Sample Sequence FIFOn 0 The fourth sample is sent to the digital comparator unit specified by the S3DCSEL bit in...

Page 1135: ...ld Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x0000 RO...

Page 1136: ...encodings as S3DCSEL but is used during the second sample 0x0 RW S1DCSEL 7 4 Sample 0 Digital Comparator Select This field has the same encodings as S3DCSEL but is used during the first sample 0x0 RW...

Page 1137: ...8 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 EMUX0 reserved EMUX1...

Page 1138: ...elect Upper Bit The EMUX1 field is used during the second sample of a sequence executed with the sample sequencer This bit has the same description as EMUX3 0x0 RW EMUX1 4 Software should not rely on...

Page 1139: ...reserved 0x7 64 0x8 reserved 0x9 128 0xA reserved 0xB 256 0xC reserved 0xD 0xF ADC Sample Sequence n Sample and Hold Time ADCSSTSHn ADC0 base 0x4003 8000 ADC1 base 0x4003 9000 Offset 0x07C Type RW re...

Page 1140: ...third sample of a sequence executed with the sample sequencer 0x0 RW TSH2 11 8 2nd Sample and Hold Period Select The TSH1 field is used during the second sample of a sequence executed with the sample...

Page 1141: ...ultiplexer Select 3 ADCSSMUX3 ADC0 base 0x4003 8000 ADC1 base 0x4003 9000 Offset 0x0A0 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO...

Page 1142: ...ely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x0000 000 RO reserved 31 4 1st Sa...

Page 1143: ...put is differentially sampled The corresponding ADCSSMUXn nibble must be set to the pair number i where the paired inputs are 2i and 2i 1 1 Because the temperature sensor does not have a differential...

Page 1144: ...10 11 12 13 14 15 S0DCOP reserved RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value...

Page 1145: ...served bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x0000 000 RO reserved 31 4 Sample 0 Digital Comparator Se...

Page 1146: ...24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 EMUX0 reserved RW RO RO RO RO RO RO RO...

Page 1147: ...ime ADCSSTSH3 ADC0 base 0x4003 8000 ADC1 base 0x4003 9000 Offset 0x0BC Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R...

Page 1148: ...with future products the value of a reserved bit should be preserved across a read modify write operation 0x00 RO reserved 31 24 Digital Comparator Trigger 7 Description Value No effect 0 Resets the...

Page 1149: ...when starting a new sequence so that stale data is not used 0 WO DCTRIG4 20 Digital Comparator Trigger 3 Description Value No effect 0 Resets the Digital Comparator 3 trigger unit to its initial condi...

Page 1150: ...alue of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x00 RO reserved 15 8 Digital Comparator Inter...

Page 1151: ...s when starting a new sequence so that stale data is not used 0 WO DCINT4 4 Digital Comparator Interrupt 3 Description Value No effect 0 Resets the Digital Comparator 3 interrupt unit to its initial c...

Page 1152: ...ns when starting a new sequence so that stale data is not used 0 WO DCINT1 1 Digital Comparator Interrupt 0 Description Value No effect 0 Resets the Digital Comparator 0 interrupt unit to its initial...

Page 1153: ...0x4003 9000 Offset 0xE00 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset...

Page 1154: ...on 0x1 Hysteresis Always This mode generates a trigger when the ADC conversion data falls within the selected operational region and continues to generate the trigger until the hysteresis condition is...

Page 1155: ...made Description Value Always This mode generates an interrupt every time the ADC conversion data falls within the selected operational region 0x0 Once This mode generates an interrupt the first time...

Page 1156: ...RW RW RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 COMP0 reserved RW RW RW RW RW RW RW RW RW RW RW RW RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 1157: ...Programmable Sample and Hold Time This bit indicates the ADC has the capability of allowing the application to adjust the sample and hold window period 0x1 RO APSHT 24 Temperature Sensor Description V...

Page 1158: ...des similar information to the legacy DC3 and DC8 register ADCnAINn bits 0x14 RO CH 9 4 Maximum Conversion Rate This field specifies the maximum value that may be programmed into the ADCPC register s...

Page 1159: ...d across a read modify write operation 0x0000 0000 RO reserved 31 4 Conversion Rate This field specifies the relative sample rate of the ADC and is used in run sleep and deep sleep modes It allows the...

Page 1160: ...RO RO RO RO RO Type 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products t...

Page 1161: ...terface characteristics 5 6 7 or 8 data bits Even odd stick or no parity bit generation detection 1 or 2 stop bit generation IrDA serial IR SIR encoder decoder providing Programmable use of IrDA Seria...

Page 1162: ...RTICR UARTDR Control Status Transmitter with SIR Transmit Encoder Baud Rate Generator UARTIBRD UARTFBRD Receiver with SIR Receive Decoder UnTx UnRx System Clock Interrupt Clock Control UARTCTL PIOSC B...

Page 1163: ...em flow control output signal TTL O PH0 1 PB5 1 29 120 U0RTS UART module 0 receive TTL I PA0 1 33 U0Rx UART module 0 transmit TTL O PA1 1 34 U0Tx UART module 1 Clear To Send modem flow control input s...

Page 1164: ...RXE bits of the UART Control UARTCTL register see page 1188 Transmit and receive are both enabled out of reset Before any control registers are programmed the UART must be disabled by clearing the UA...

Page 1165: ...the system clock PLL settings See the UARTCC register for more details The 6 bit fractional number that is to be loaded into the DIVFRAC bit field in the UARTFBRD register can be calculated by taking...

Page 1166: ...hat word 16 3 4 Serial IR SIR The UART peripheral includes an IrDA serial IR SIR encoder decoder block The IrDA SIR block provides functionality that converts between an asynchronous UART data stream...

Page 1167: ...ter LED This delay is known as latency or receiver setup time 16 3 5 ISO 7816 Support The UART offers basic support to allow communication with an ISO 7816 smartcard When bit 3 SMART of the UARTCTL re...

Page 1168: ...Indicator are not provided If these signals are required their function can be emulated by using a general purpose I O signal and providing software support 16 3 6 2 Flow Control Flow control can be a...

Page 1169: ...RT9BITADDR register The matching can be extended to a set of addresses using the address mask in the UART9BITAMASK register By default the UART9BITAMASK is 0xFF meaning that only the specified address...

Page 1170: ...gle interrupt service routine by reading the UART Masked Interrupt Status UARTMIS register see page 1202 The interrupt events that can trigger a controller level interrupt are defined in the UART Inte...

Page 1171: ...request is asserted whenever any data is in the receive FIFO A burst transfer request is asserted whenever the amount of data in the receive FIFO is at or above the FIFO trigger level configured in th...

Page 1172: ...e 26 5 on page 1808 This section discusses the steps that are required to use a UART module For this example the UART clock is assumed to be 20 MHz and the desired UART configuration is 115200 baud ra...

Page 1173: ...delay of 3 system clocks after the UART module clock is enabled before any UART module registers are accessed The UART must be disabled see the UARTEN bit in the UARTCTL register on page 1188 before a...

Page 1174: ...CC 0xFC8 1214 UART Peripheral Identification 4 0x0000 0060 RO UARTPeriphID4 0xFD0 1215 UART Peripheral Identification 5 0x0000 0000 RO UARTPeriphID5 0xFD4 1216 UART Peripheral Identification 6 0x0000...

Page 1175: ...ART0 base 0x4000 C000 UART1 base 0x4000 D000 UART2 base 0x4000 E000 UART3 base 0x4000 F000 UART4 base 0x4001 0000 UART5 base 0x4001 1000 UART6 base 0x4001 2000 UART7 base 0x4001 3000 Offset 0x000 Type...

Page 1176: ...bit is received 0 RO BE 10 UART Parity Error Description Value No parity error has occurred 0 The parity of the received data character does not match the parity defined by bits 2 and 7 of the UARTLCR...

Page 1177: ...01 3000 Offset 0x004 Type RO reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2...

Page 1178: ...ed to 0 by a write to UARTECR 0 RO PE 1 UART Framing Error Description Value No framing error has occurred 0 The received character does not have a valid stop bit a valid stop bit is 1 1 This bit is c...

Page 1179: ...ure products the value of a reserved bit should be preserved across a read modify write operation 0x0000 00 WO reserved 31 8 Error Clear A write to this register of any data clears the framing parity...

Page 1180: ...x018 Type RO reset 0x0000 0090 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 1...

Page 1181: ...er is full If the FIFO is enabled FEN is 1 the receive FIFO is full 1 0 RO RXFF 6 UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register Descripti...

Page 1182: ...pty regardless of whether UART is enabled 0 RO BUSY 3 Data Carrier Detect Description Value The UnDCD signal is not asserted 0 The UnDCD signal is asserted 1 0 RO DCD 2 Data Set Ready Description Valu...

Page 1183: ...period of IrLPBaud16 are rejected but pulses greater than 1 4 s are accepted as valid pulses Note Zero is an illegal value Programming a zero value results in no IrLPBaud16 pulses being generated UART...

Page 1184: ...base 0x4000 E000 UART3 base 0x4000 F000 UART4 base 0x4001 0000 UART5 base 0x4001 1000 UART6 base 0x4001 2000 UART7 base 0x4001 3000 Offset 0x024 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25...

Page 1185: ...base 0x4001 0000 UART5 base 0x4001 1000 UART6 base 0x4001 2000 UART7 base 0x4001 3000 Offset 0x028 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO...

Page 1186: ...eset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BRK PEN EPS STP2 FEN WLEN SPS reserved RW RW RW RW RW RW RW RW RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name...

Page 1187: ...ue Odd parity is performed which checks for an odd number of 1s 0 Even parity generation and checking is performed during transmission and reception which checks for an even number of 1s in data and p...

Page 1188: ...e the results are unpredictable The following sequence is recommended for making changes to the UARTCTL register 1 Disable the UART 2 Wait for the end of transmission or reception of the current chara...

Page 1189: ...across a read modify write operation 0 RO reserved 13 12 Request to Send When RTSEN is clear the status of this bit is reflected on the U1RTS signal If RTSEN is set this bit is ignored on a write and...

Page 1190: ...the TXRIS bit in the UARTRIS register Description Value The TXRIS bit is set when the transmit FIFO condition specified in UARTIFLS is met 0 The TXRIS bit is set only after all transmitted data inclu...

Page 1191: ...ted bit rate 1 Setting this bit uses less power but might reduce transmission distances See page 1183 for more information 0 RW SIRLP 2 UART SIR Enable Description Value Normal operation 0 The IrDA SI...

Page 1192: ...000 UART4 base 0x4001 0000 UART5 base 0x4001 1000 UART6 base 0x4001 2000 UART7 base 0x4001 3000 Offset 0x034 Type RW reset 0x0000 0012 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO...

Page 1193: ...default 0x2 TX FIFO empty 0x3 TX FIFO empty 0x4 Reserved 0x5 0x7 Note If the EOT bit in UARTCTL is set see page 1188 the transmit interrupt is generated once the FIFO is completely empty and all data...

Page 1194: ...00 UART7 base 0x4001 3000 Offset 0x038 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 DMARXIM DMATXIM reserved RW RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0...

Page 1195: ...TRIS bit in the UARTRIS register is set 1 0 RW 9BITIM 12 End of Transmission Interrupt Mask Description Value The EOTRIS interrupt is suppressed and not sent to the interrupt controller 0 An interrupt...

Page 1196: ...ller when the RTRIS bit in the UARTRIS register is set 1 0 RW RTIM 6 UART Transmit Interrupt Mask Description Value The TXRIS interrupt is suppressed and not sent to the interrupt controller 0 An inte...

Page 1197: ...ption Value The CTSRIS interrupt is suppressed and not sent to the interrupt controller 0 An interrupt is sent to the interrupt controller when the CTSRIS bit in the UARTRIS register is set 1 0 RW CTS...

Page 1198: ...RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future prod...

Page 1199: ...has occurred 1 This bit is cleared by writing a 1 to the OEIC bit in the UARTICR register 0 RO OERIS 10 UART Break Error Raw Interrupt Status Description Value No interrupt 0 A break error has occurr...

Page 1200: ...by writing a single byte if the FIFO is disabled 0 RO TXRIS 5 UART Receive Raw Interrupt Status Description Value No interrupt 0 The receive FIFO level has passed through the condition defined in the...

Page 1201: ...eared by writing a 1 to the CTSIC bit in the UARTICR register 0 RO CTSRIS 1 UART Ring Indicator Modem Raw Interrupt Status Description Value No interrupt 0 Ring Indicator used for software flow contro...

Page 1202: ...ion Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify...

Page 1203: ...ror 1 This bit is cleared by writing a 1 to the OEIC bit in the UARTICR register 0 RO OEMIS 10 UART Break Error Masked Interrupt Status Description Value An interrupt has not occurred or is masked 0 A...

Page 1204: ...is disabled 0 RO TXMIS 5 UART Receive Masked Interrupt Status Description Value An interrupt has not occurred or is masked 0 An unmasked interrupt was signaled due to passing through the specified rec...

Page 1205: ...eared by writing a 1 to the CTSIC bit in the UARTICR register 0 RO CTSMIS 1 UART Ring Indicator Modem Masked Interrupt Status Description Value An interrupt has not occurred or is masked 0 An unmasked...

Page 1206: ...bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 RO reserved 31 18 Transmit DMA Interrupt Clear Writing a 1 to t...

Page 1207: ...IS bit in the UARTMIS register 0 W1C TXIC 5 Receive Interrupt Clear Writing a 1 to this bit clears the RXRIS bit in the UARTRIS register and the RXMIS bit in the UARTMIS register 0 W1C RXIC 4 UART Dat...

Page 1208: ...0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit sho...

Page 1209: ...Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ADDR reserved 9BITEN RW RW RW RW RW RW RW RW RO RO RO RO RO RO RO RW Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Softw...

Page 1210: ...28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MASK reserved RW RW RW RW RW RW RW RW RO RO RO RO...

Page 1211: ...re should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x0 RO reserved 31...

Page 1212: ...ard Support Description Value The UART module does not provide smart card support 0 The UART module provides smart card support 1 0x1 RO SC 0 June 18 2014 1212 Texas Instruments Production Data Univer...

Page 1213: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CS reserved RW RW RW RW RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type...

Page 1214: ...O RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PID4 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0...

Page 1215: ...served RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PID5 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Ty...

Page 1216: ...RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PID6 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0...

Page 1217: ...served RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PID7 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Ty...

Page 1218: ...O RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PID0 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 0 0...

Page 1219: ...served RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PID1 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Ty...

Page 1220: ...RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PID2 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0...

Page 1221: ...served RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PID3 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Ty...

Page 1222: ...RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CID0 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 0 1 1...

Page 1223: ...rved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CID1 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type...

Page 1224: ...O RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CID2 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 0 1 0...

Page 1225: ...rved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CID3 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type...

Page 1226: ...anced Bi and Quad SSI functionality Programmable interface operation for Freescale SPI or Texas Instruments synchronous serial interfaces in Legacy Mode Support for Freescale interface in Bi and Quad...

Page 1227: ...IIM SSIICR Clock Control SSICC SSI Baud Clock SSInXDAT2 SSInXDAT3 SSInXDAT0 TX SSInXDAT1 RX ALTCLK 17 2 Signal Description The following table lists the external signals of the QSSI module and describ...

Page 1228: ...gacy SSI Mode TTL I O PE5 15 124 SSI1XDAT1 SSI Module 1 Bi directional Data Pin 2 TTL I O PD4 15 125 SSI1XDAT2 SSI Module 1 Bi directional Data Pin 3 TTL I O PD5 15 126 SSI1XDAT3 SSI module 2 clock TT...

Page 1229: ...rface SSI on page 1867 to view legacy SSI and QSSI timing parameters 17 3 2 FIFO Operation 17 3 2 1 Transmit FIFO The common transmit FIFO is a 16 bit wide 8 locations deep first in first out memory b...

Page 1230: ...ntry bits 7 0 and the mode of operation is inserted in the three most significant bits of the TX FIFO entry The mode of operation bits 15 13 in the TX FIFO are used by the QSSI module for configuring...

Page 1231: ...in a single transaction 17 3 4 SSInFSS Function For enhanced modes of operation the SSInFss signal can be programmed to assert low at the start of each byte transfer for one clock or the entire frame...

Page 1232: ...an generate interrupts when the following conditions are observed Transmit FIFO service when the transmit FIFO is half full or less Receive FIFO service when the receive FIFO is half full or more Rece...

Page 1233: ...bits long in Legacy mode and 8 bits in Advanced Bi Quad SSI mode and is transmitted starting with the MSB There are two basic frame types that can be selected by programming the FRF bit in the SSICR0...

Page 1234: ...transmit data line SSInDAT0 SSInTX is tristated whenever the QSSI is idle Once the bottom entry of the transmit FIFO contains data SSInFss is pulsed High for one SSInClk period The value to be transm...

Page 1235: ...the SSInClk pin when data is not being transferred SPH Phase Control Bit The SPH phase control bit selects the clock edge that captures data and allows it to change state The state of this bit has the...

Page 1236: ...red as a slave it disables the SSInClk pad If the QSSI is enabled and valid data is in the transmit FIFO the start of transmission is signified by the SSInFss master signal being driven Low causing sl...

Page 1237: ...th single and continuous transfers Note This Freescale SPI frame format configuration is only available when operating in Legacy SSI mode of operation Figure 17 6 Freescale SPI Frame Format with SPO 0...

Page 1238: ...his Freescale SPI frame format configuration is only available when operating in Legacy SSI mode of operation Figure 17 7 Freescale SPI Frame Format Single Transfer with SPO 1 and SPH 0 SSInClk SSInFs...

Page 1239: ...ripheral register and does not allow it to be altered if the SPH bit is clear Therefore the master device must raise the SSInFss pin of the slave device between each data transfer to enable the serial...

Page 1240: ...is in the transmit FIFO The burst request is asserted whenever the transmit FIFO has 4 or more empty slots The single and burst DMA transfer requests are handled automatically by the DMA controller de...

Page 1241: ...Select GPIOPUR register For each of the frame formats the QSSI is configured using the following steps 1 If initializing out of reset ensure that the SSE bit in the SSICR1 register is clear before ma...

Page 1242: ...ase if CPSDVSR 0x2 SCR must be 0x9 The configuration sequence would be as follows 1 Ensure that the SSE bit in the SSICR1 register is clear 2 Write the SSICR1 register with a value of 0x0000 0000 3 Wr...

Page 1243: ...rol 0 0x0000 0000 RW SSICR0 0x000 1247 QSSI Control 1 0x0000 0000 RW SSICR1 0x004 1249 QSSI Data 0x0000 0000 RW SSIDR 0x008 1250 QSSI Status 0x0000 0003 RO SSISR 0x00C 1252 QSSI Clock Prescale 0x0000...

Page 1244: ...1 QSSI PrimeCell Identification 0 0x0000 000D RO SSIPCellID0 0xFF0 1272 QSSI PrimeCell Identification 1 0x0000 00F0 RO SSIPCellID1 0xFF4 1273 QSSI PrimeCell Identification 2 0x0000 0005 RO SSIPCellID2...

Page 1245: ...s bit field is used to generate the transmit and receive bit rate of the QSSI The bit rate is BR SysClk CPSDVSR 1 SCR where CPSDVSR is an even value from 2 254 programmed in the SSICPSR register and S...

Page 1246: ...2 0x3 0x0 RW FRF 5 4 QSSI Data Size Select Note When operating in Advanced Bi or Quad SSI data size can only be 8 bit All other fields will be ignored Data Size Value Reserved 0x0 0x2 4 bit data 0x3 5...

Page 1247: ...it should be preserved across a read modify write operation 0x0000 0 RO reserved 31 12 Stop Frame End of Message This bit is applicable when MODE is set to Advanced Bi or Quad SSI This bit is inserted...

Page 1248: ...SSE 0 Description Value The QSSI is configured as a master 0 The QSSI is configured as a slave 1 0 RW MS 2 QSSI Synchronous Serial Port Enable Description Value QSSI operation is disabled 0 QSSI oper...

Page 1249: ...ess than 16 bits is automatically right justified in the receive buffer QSSI Data SSIDR QSSI0 base 0x4000 8000 QSSI1 base 0x4000 9000 QSSI2 base 0x4000 A000 QSSI3 base 0x4000 B000 Offset 0x008 Type RW...

Page 1250: ...Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x...

Page 1251: ...pe Name Bit Field QSSI Transmit FIFO Empty Description Value The transmit FIFO is not empty 0 The transmit FIFO is empty 1 1 RO TFE 0 1251 June 18 2014 Texas Instruments Production Data Tiva TM4C1294N...

Page 1252: ...0 QSSI2 base 0x4000 A000 QSSI3 base 0x4000 B000 Offset 0x010 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0...

Page 1253: ...DMATXIM EOTIM reserved RW RW RW RW RW RW RW RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reser...

Page 1254: ...t Interrupt Mask Description Value The receive FIFO time out interrupt is masked 0 The receive FIFO time out interrupt is not masked 1 0 RW RTIM 1 QSSI Receive Overrun Interrupt Mask Description Value...

Page 1255: ...d not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 RO reserved 31 7 End of T...

Page 1256: ...FIFO is less than half full 0 RO RXRIS 2 QSSI Receive Time Out Raw Interrupt Status Description Value No interrupt 0 The receive time out has occurred 1 This bit is cleared when a 1 is written to the...

Page 1257: ...ue of a reserved bit should be preserved across a read modify write operation 0 RO reserved 31 7 End of Transmit Masked Interrupt Status Description Value An interrupt has not occurred or is masked 0...

Page 1258: ...the receive FIFO is less than half full 0 RO RXMIS 2 QSSI Receive Time Out Masked Interrupt Status Description Value An interrupt has not occurred or is masked 0 An unmasked interrupt was signaled du...

Page 1259: ...erved 31 7 End of Transmit Interrupt Clear Writing a 1 to this bit clears the EOTRIS bit in the SSIRIS register and the EOTMIS bit in the SSIMIS register 0 W1C EOTIC 6 QSSI Transmit DMA Interrupt Clea...

Page 1260: ...RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility wi...

Page 1261: ...t Field Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x000...

Page 1262: ...CS reserved RW RW RW RW RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To...

Page 1263: ...RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PID4 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Descrip...

Page 1264: ...O RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PID5 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Descripti...

Page 1265: ...RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PID6 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Descript...

Page 1266: ...RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PID7 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Descriptio...

Page 1267: ...RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PID0 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 Reset Descrip...

Page 1268: ...O RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PID1 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Descripti...

Page 1269: ...RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PID2 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 Reset Descript...

Page 1270: ...RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PID3 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Descriptio...

Page 1271: ...O RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CID0 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 Reset Descripti...

Page 1272: ...RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CID1 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 Reset Description...

Page 1273: ...RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CID2 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Descriptio...

Page 1274: ...O Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CID3 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 Reset Description...

Page 1275: ...tures Devices on the I2 C bus can be designated as either a master or a slave Supports both transmitting and receiving data as either a master or a slave Supports simultaneous master and slave operati...

Page 1276: ...e RX and TX FIFOs in the I2 C 18 1 Block Diagram Figure 18 1 I2 C Block Diagram I2CSDA I2CSCL I2CPP I2CFIFOSTATUS I2CFIFOCTL I2CFIFODATA I2CMSA I2CMCS I2CMDR I2CMTPR I2CMIMR I2CMRIS I2CMICR I2CMCR I2C...

Page 1277: ...nding port pin should not be configured as open drain OD I O PG0 2 49 I2C1SCL I2 C module 1 data OD I O PG1 2 50 I2C1SDA I2 C module 2 clock Note that this signal has an active pull up The correspondi...

Page 1278: ...Figure 18 2 Refer to the I2C bus specification and user manual to determine the size of the pull ups needed for proper operation See Inter Integrated Circuit I2 C Interface on page 1870 for I2 C timi...

Page 1279: ...r When operating in slave mode the STARTRIS and STOPRIS bits in the I2 C Slave Raw Interrupt Status I2CSRIS register indicate detection of start and stop conditions on the bus and the I2 C Slave Maske...

Page 1280: ...ndition and abort the current transfer If the master device is acting as a receiver during a transfer it is responsible for acknowledging each transfer made by the slave Because the master controls th...

Page 1281: ...ount is loaded at the START condition and counts down on each falling edge of the internal bus clock of the Master Note that the internal bus clock generated for this counter keeps running at the prog...

Page 1282: ...address disabled the I2 C slave provides an ACK on the bus if the address matches the OAR field in the I2CSOAR register In dual address mode the I2 C slave provides an ACK on the bus if either the OAR...

Page 1283: ...ny issues with the transfer In addition the slave can send a NACK at any time to force the master to stop sending additional bytes The I2 C Interface supports DMA for efficient data handling The DMA o...

Page 1284: ...se of SCL fixed at 6 SCL_HP is the high phase of SCL fixed at 4 TIMER_PRD is the programmed value in the I2CMTPR register see page 1313 This value is determined by replacing the known variables in the...

Page 1285: ...ns TIMER_PRD 1 SCL_LP 2 SCL_HP 1 yields a SCL frequency of 1 T 3 33 Mhz Table 18 3 on page 1285 gives examples of timer period and system clock in High Speed mode Note that the HS bit in the I2CMTPR r...

Page 1286: ...lock frequency is set and there is appropriate pull strength on SCL and SDA lines 18 3 3 Interrupts The I2 C can generate interrupts when the following conditions are observed in the Master Module Mas...

Page 1287: ...ansaction 18 3 4 Loopback Operation The I2 C modules can be placed into an internal loopback mode for diagnostic or debug work by setting the LPBK bit in the I2 C Master Configuration I2CMCR register...

Page 1288: ...ionality When the Master Control Status I2CMCS register is set to enable BURST and the master I2 C DMA channel is enabled in the DMA Channel Map Select n DMACHMAPn registers in the DMA the master cont...

Page 1289: ...the capability to use the DMA in Rx and Tx FIFO data transfers If the Tx FIFO is assigned to the slave module and the TXFIFO bit is set in the I2CSCSR register the slave module will generate a single...

Page 1290: ...ata to I2CMDR Read I2CMCS Sequence may be omitted in a Single Master system BUSBSY bit 0 NO Write 0 111 to I2CMCS YES Read I2CMCS BUSY bit 0 ERROR bit 0 YES Error Service Idle YES NO NO June 18 2014 1...

Page 1291: ...2CMCS Sequence may be omitted in a Single Master system BUSBSY bit 0 NO Write 00111 to I2CMCS YES Read I2CMCS BUSY bit 0 ERROR bit 0 YES Error Service Idle NO NO Read data from I2CMDR YES 1291 June 18...

Page 1292: ...t 0 YES ERROR bit 0 YES ARBLST bit 1 Write data to I2CMDR Write 0 100 to I2CMCS Index n NO Error Service Idle YES Write 0 001 to I2CMCS Write 0 101 to I2CMCS YES Read I2CMCS BUSY bit 0 ERROR bit 0 YES...

Page 1293: ...YES ARBLST bit 1 Write 0 100 to I2CMCS NO Error Service YES Idle Read data from I2CMDR Index m 1 Write 00101 to I2CMCS YES Idle Read data from I2CMDR Error Service ERROR bit 0 YES Write 01001 to I2CMC...

Page 1294: ...Transmit mode STOP condition is not generated Write Slave Address to I2CMSA Write 01011 to I2CMCS Master operates in Master Receive mode Idle Repeated START condition is generated with changing data d...

Page 1295: ...er Receive mode STOP condition is not generated Write Slave Address to I2CMSA Write 0 011 to I2CMCS Master operates in Master Transmit mode Idle Repeated START condition is generated with changing dat...

Page 1296: ...o I2MSA register write Data to I2CMDR register yes yes no no Normal sequence starts here The sequence below covers SINGLE send write 0 111 to I2CMCS register read I2CMCS register Busy 0 Error 0 IDLE y...

Page 1297: ...how to configure the I2 C module to transmit a single byte as a master This assumes the system clock is 20 MHz 1 Enable the I2 C clock using the RCGCI2C register in the System Control module see page...

Page 1298: ...ing the I2CMCS register s BUSBSY bit until it has been cleared 12 Check the ERROR bit in the I2CMCS register to confirm the transmit was acknowledged 18 4 2 Configure the I2 C Master to High Speed Mod...

Page 1299: ...he I2CMCS register s BUSBSY bit until it has been cleared 12 Check the ERROR bit in the I2CMCS register to confirm the transmit was acknowledged 18 5 Register Map Table 18 4 on page 1300 lists the I2...

Page 1300: ...0 0000 RW I2CMBLEN 0x030 1330 I2C Master Burst Count 0x0000 0000 RO I2CMBCNT 0x034 I2 C Slave 1331 I2C Slave Own Address 0x0000 0000 RW I2CSOAR 0x800 1332 I2C Slave Control Status 0x0000 0000 RO I2CSC...

Page 1301: ...iptions I2 C Master The remainder of this section lists and describes the I2 C master registers in numerical order by address offset 1301 June 18 2014 Texas Instruments Production Data Tiva TM4C1294NC...

Page 1302: ...O RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R S SA reserved RW RW RW RW RW RW RW RW RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 1303: ...to transmit an acknowledge automatically after each byte This bit must be cleared when the I2 C bus controller requires no further data to be transmitted from the slave transmitter Read Only Status R...

Page 1304: ...s idle 0 The I2 C bus is busy 1 The bit changes based on the START and STOP conditions 0 RO BUSBSY 6 I2 C Idle Description Value The I2 C controller is not idle 0 The I2 C controller is idle 1 1 RO ID...

Page 1305: ...4 Type WO reset 0x0000 0020 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 1...

Page 1306: ...eed mode with transmission speeds up to 3 33 Mbps 1 0 WO HS 4 Data Acknowledge Enable Description Value The received data byte is not acknowledged automatically by the master 0 The received data byte...

Page 1307: ...master is able to transmit or receive data Note that this bit cannot be set in Burst mode See field decoding in Table 18 5 on page 1308 1 Note that the BURST and RUN bits are mutually exclusive 0 WO...

Page 1308: ...RECEIVE and STOP condition master remains in Idle state 1 1 1 0 0 0 0 1 START condition followed by RECEIVE master goes to the Master Receive state 1 1 0 1 0 0 0 1 START condition followed by N FIFO s...

Page 1309: ...0 X 0 0 1 0 Repeated START condition followed by N FIFO serviced TRANSMIT operations and STOP condition master goes to Idle state 0 1 1 X 0 0 1 0 Repeated START condition followed by a RECEIVE operati...

Page 1310: ...er goes to Idle state 1 1 1 0 0 0 0 1 Repeated START condition followed by RECEIVE master remains in Master Receive state 1 1 0 1 0 0 0 1 Repeated START condition followed by N FIFO serviced RECEIVE o...

Page 1311: ...ndition should be generated only after a Data Negative Acknowledge executed by the master or an Address Negative Acknowledge executed by the slave 1311 June 18 2014 Texas Instruments Production Data T...

Page 1312: ...2C 7 base 0x400C 3000 I2C 8 base 0x400B 8000 I2C 9 base 0x400B 9000 Offset 0x008 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO...

Page 1313: ...RO Type 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the value of...

Page 1314: ...x0 WO HS 7 Timer Period This field is used in the equation to configure SCL_PERIOD SCL_PERIOD 2 1 TPR SCL_LP SCL_HP CLK_PRD where SCL_PRD is the SCL line period I2 C clock TPR is the Timer Period regi...

Page 1315: ...Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 RO reserve...

Page 1316: ...r when the ARBLOSTRIS bit in the I2CMRIS register is set 1 0 RW ARBLOSTIM 7 STOP Detection Interrupt Mask Description Value The STOPRIS interrupt is suppressed and not sent to the interrupt controller...

Page 1317: ...to the interrupt controller when the DMARXRIS bit in the I2CMRIS register is set 1 0 RW DMARXIM 2 Clock Timeout Interrupt Mask Description Value The CLKRIS interrupt is suppressed and not sent to the...

Page 1318: ...0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit shou...

Page 1319: ...Status Description Value No interrupt 0 The Arbitration Lost interrupt is pending 1 This bit is cleared by writing a 1 to the ARBLOSTIC bit in the I2CMICR register 0 RO ARBLOSTRIS 7 STOP Detection Raw...

Page 1320: ...e DMARXIC bit in the I2CMICR register 0 RO DMARXRIS 2 Clock Timeout Raw Interrupt Status Description Value No interrupt 0 The clock timeout interrupt is pending 1 This bit is cleared by writing a 1 to...

Page 1321: ...MIS RXFFMIS reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserve...

Page 1322: ...ption Value No interrupt 0 An unmasked Arbitration Lost interrupt was signaled and is pending 1 This bit is cleared by writing a 1 to the ARBLOSTIC bit in the I2CMICR register 0 RO ARBLOSTMIS 7 STOP D...

Page 1323: ...on Value No interrupt 0 An unmasked receive DMA complete interrupt was signaled and is pending 1 This bit is cleared by writing a 1 to the DMARXIC bit in the I2CMICR register 0 RO DMARXMIS 2 Clock Tim...

Page 1324: ...operation 0 RO reserved 31 12 Receive FIFO Full Interrupt Clear Writing a 1 to this bit clears the RXFFIS bit in the I2CMRIS register and the RXFFMIS bit in the I2CMMIS register A read of this registe...

Page 1325: ...terrupt Clear Writing a 1 to this bit clears the DMATXRIS bit in the I2CMRIS register and the DMATXMIS bit in the I2CMMIS register A read of this register returns no meaningful data 0 WO DMATXIC 3 Rec...

Page 1326: ...e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reser...

Page 1327: ...1000 I2C 6 base 0x400C 2000 I2C 7 base 0x400C 3000 I2C 8 base 0x400B 8000 I2C 9 base 0x400B 9000 Offset 0x024 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO R...

Page 1328: ...pe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCL SDA reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description R...

Page 1329: ...RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CNTL reserved RW RW RW RW RW RW RW RW RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Re...

Page 1330: ...7 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CNTL reserved RO R...

Page 1331: ...7 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 OAR reserved RW RW RW RW RW RW RW RO RO RO RO RO...

Page 1332: ...9 10 11 12 13 14 15 RREQ TREQ FBR OAR2SEL QCMDST QCMDRW reserved RO RO RO RO RC RC RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field DMA RX...

Page 1333: ...eceived 1 This bit is only valid when the RREQ bit is set and is automatically cleared when data has been read from the I2CSDR register Note This bit is not used for slave transmit operations 0 RO FBR...

Page 1334: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bi...

Page 1335: ...4 base 0x400C 0000 I2C 5 base 0x400C 1000 I2C 6 base 0x400C 2000 I2C 7 base 0x400C 3000 I2C 8 base 0x400B 8000 I2C 9 base 0x400B 9000 Offset 0x808 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24...

Page 1336: ...value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 RO reserved 31 9 Receive FIFO Full Interru...

Page 1337: ...to the interrupt controller when the DMARXRIS bit in the I2CSRIS register is set 1 0 RW DMARXIM 3 Stop Condition Interrupt Mask Description Value The STOPRIS interrupt is suppressed and not sent to t...

Page 1338: ...0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be prese...

Page 1339: ...A complete interrupt is pending 1 This bit is cleared by writing a 1 to the DMATXIC bit in the I2CSICR register 0 RO DMATXRIS 4 Receive DMA Raw Interrupt Status Description Value No interrupt 0 A rece...

Page 1340: ...action received Slave transaction requested Next byte transfer request Description Value No interrupt 0 Slave Interrupt is pending 1 This bit is cleared by writing a 1 to the DATAIC bit in the I2CSICR...

Page 1341: ...S reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To p...

Page 1342: ...is masked 0 An unmasked transmit DMA complete interrupt was signaled is pending 1 This bit is cleared by writing a 1 to the DMATXIC bit in the I2CSICR register 0 RO DMATXMIS 4 Receive DMA Masked Inte...

Page 1343: ...is cleared by writing a 1 to the STARTIC bit in the I2CSICR register 0 RO STARTMIS 1 Data Masked Interrupt Status Description Value An interrupt has not occurred or is masked 0 An unmasked slave data...

Page 1344: ...ss a read modify write operation 0 RO reserved 31 9 Receive FIFO Full Interrupt Mask Writing a 1 to this bit clears the RXFFIS bit in the I2CSRIS register and the RXFFMIS bit in the I2CSMIS register A...

Page 1345: ...SMIS register A read of this register returns no meaningful data 0 WO STOPIC 2 Start Condition Interrupt Clear Writing a 1 to this bit clears the STARTRIS bit in the I2CSRIS register and the STARTMIS...

Page 1346: ...pe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 OAR2 OAR2EN reserved RW RW RW RW RW RW RW RW RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Descripti...

Page 1347: ...L reserved RW RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To p...

Page 1348: ...2 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DATA reserved RO RO RO RO RO RO R...

Page 1349: ...11 12 13 14 15 DATA reserved WO WO WO WO WO WO WO WO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of...

Page 1350: ...0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TXTRIG reserved DMATXENA TXFLUSH TXASGNMT RW RW RW RO RO RO RO RO RO RO RO RO RO RW RW RW Type 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset...

Page 1351: ...1 0 RW TXASGNMT 15 TX FIFO Flush Setting this bit will Flush the TX FIFO This bit will self clear when the flush has completed 0 RW TXFLUSH 14 DMA TX Channel Enable Description Value DMA TX channel d...

Page 1352: ...e should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x000 RO reserved 31...

Page 1353: ...number of bytes in the TX FIFO is below the trigger level programmed by the TXTRIG bit in the I2CFIFOCTL register 1 1 RO TXBLWTRIG 2 TX FIFO Full Description Value The TX FIFO is not full 0 The TX FIF...

Page 1354: ...RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 HS reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 1355: ...0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 HS reserved RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Sof...

Page 1356: ...k lengths less than 40 meters Decreased bit rates allow longer network distances for example 125 Kbps at 500 meters The TM4C1294NCPDT microcontroller includes two CAN units with the following features...

Page 1357: ...N controller signals are alternate functions for some GPIO signals and default to be GPIO signals at reset The column in the table below titled Pin Mux Pin Assignment lists the possible GPIO pin place...

Page 1358: ...s no data and is used to request the transmission of a specific message object The CAN data remote frame is constructed as shown in Figure 19 2 Figure 19 2 CAN Data Remote Frame Number Of Bits S O F E...

Page 1359: ...er set the CAN Bit Timing CANBIT register and configure each message object If a message object is not needed label it as not valid by clearing the MSGVAL bit in the CAN IFn Arbitration 2 CANIFnARB2 r...

Page 1360: ...y by the reception of a remote frame with a matching identifier Transmission can be automatically started by the reception of a matching remote frame To enable this mode set the RMTEN bit in the CAN I...

Page 1361: ...to specify which of the bits in the 29 bit or 11 bit message identifier are used for acceptance filtering Note that MSK 12 0 are used for bits 28 16 of the 29 bit message identifier whereas MSK 12 2...

Page 1362: ...FnDAn CANIFnDBn register before the CPU writes the new data bytes In order to only update the data in a message object the WRNRD DATAA and DATAB bits in the CANIFnMSKn register are set followed by wri...

Page 1363: ...object as soon as possible DIR 1 direction transmit programmed in the CANIFnARB2 register RMTEN 1 set the TXRQST bit of the CANIFnMCTL register at reception of the frame to enable transmission UMASK...

Page 1364: ...tance filtering Also note that in order for these bits to be used for acceptance filtering they must be enabled by setting the UMASK bit in the CANIFnMCTL register 4 Program the CANIFnARB1 and CANIFnA...

Page 1365: ...frame triggers the other CAN node to start the transmission of the matching data frame If the matching data frame is received before the remote frame could be transmitted the TXRQST bit is automatical...

Page 1366: ...assure the correct function of a FIFO buffer the CPU should read out the message objects starting with the message object with the lowest message number When reading from the FIFO buffer the user shou...

Page 1367: ...errupt Pointer Status Change Interrupt Handling END Message Interrupt Yes MNUM MNUM 1 Case Interrupt Pointer else 0x0000 0x8000 No 19 3 12 Handling of Interrupts If several interrupts are pending the...

Page 1368: ...and LEC bits in that same register however the only way to clear the source of a status interrupt is to read the CANSTS register The source of an interrupt can be determined in two ways during interru...

Page 1369: ...CAN bus is idle the CANIF1 registers are loaded into the shift register of the CAN Controller and transmission is started When the transmission has completed the BUSY bit is cleared and the locked CA...

Page 1370: ...or voltage and by deteriorating components these oscillators are not absolutely stable As long as the variations remain inside a specific oscillator s tolerance range the CAN nodes are able to compen...

Page 1371: ...in two register bytes in the CANBIT register In the CANBIT register the four components TSEG2 TSEG1 SJW and BRP have to be programmed to a numerical value that is one less than its functional value so...

Page 1372: ...it time The resulting bit time 1 bit rate must be an integer multiple of the system clock period The bit time may consist of 4 to 25 time quanta Several combinations may lead to the required bit time...

Page 1373: ...west tolerance range The calculation may show that bus length or bit rate have to be decreased or that the oscillator frequencies stability has to be increased in order to find a protocol compliant co...

Page 1374: ...ency of the CAN clock is 50 MHz and the bit rate is 100 Kbps bit time 10 s n tq 10 tq tq 1 s tq Baud rate Prescaler CAN Clock Baud rate Prescaler tq CAN Clock Baud rate Prescaler 1E 6 50E6 50 tSync 1...

Page 1375: ...the registers can be programmed see page 395 There must be a delay of 3 system clocks after the CAN module clock is enabled before any CAN module registers are accessed Table 19 5 CAN Register Map See...

Page 1376: ...97 CAN IF2 Arbitration 2 0x0000 0000 RW CANIF2ARB2 0x094 1399 CAN IF2 Message Control 0x0000 0000 RW CANIF2MCTL 0x098 1402 CAN IF2 Data A1 0x0000 0000 RW CANIF2DA1 0x09C 1402 CAN IF2 Data A2 0x0000 00...

Page 1377: ...the Message RAM CANIF1x and CANIF2x The function of the two sets are identical and are used to queue transactions 1377 June 18 2014 Texas Instruments Production Data Tiva TM4C1294NCPDT Microcontroller...

Page 1378: ...RW reset 0x0000 0001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13...

Page 1379: ...an interrupt 1 0 RW EIE 3 Status Interrupt Enable Description Value No status interrupt is generated 0 An interrupt is generated when a message has successfully been transmitted or received or a CAN b...

Page 1380: ...the CAN Interrupt CANINT register if it is pending CAN Status CANSTS CAN0 base 0x4004 0000 CAN1 base 0x4004 1000 Offset 0x004 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31...

Page 1381: ...cessfully received 0 Since this bit was last cleared a message has been successfully received independent of the result of the acceptance filtering 1 This bit must be cleared by writing a 0 to it 0 RW...

Page 1382: ...red errors A Bit 1 Error indicates that the device wanted to send a High level logical 1 but the monitored bus value was Low logical 0 0x4 Bit 0 Error A Bit 0 Error indicates that the device wanted to...

Page 1383: ...ption Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modi...

Page 1384: ...hase2 see Figure 19 4 on page 1371 The bit time quanta is defined by the BRP field 0x2 RW TSEG2 14 12 Time Segment Before Sample Point 0x00 0x0F The actual interpretation by the hardware of this value...

Page 1385: ...x4004 1000 Offset 0x010 Type RO reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0...

Page 1386: ...on Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify...

Page 1387: ...stead monitors the bus This mode is also known as Bus Monitor mode 1 0 RW SILENT 3 Basic Mode Description Value Basic mode is disabled 0 Basic mode is enabled In basic mode software should use the CAN...

Page 1388: ...2 3 4 5 6 7 8 9 10 11 12 13 14 15 BRPE reserved RW RW RW RW RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not re...

Page 1389: ...0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit sh...

Page 1390: ...INTPND CONTROL ARB MASK WRNRD reserved RW RW RW RW RW RW RW RW RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the...

Page 1391: ...ge buffer Note the value of this bit that is transferred to the CANIFnMCTL register always reflects the status of the bits before clearing If WRNRD is set the INTPND bit is cleared in the message obje...

Page 1392: ...bytes 0 3 in message object to CANIFnDA1 and CANIFnDA2 1 0 RW DATAA 1 Access Data Byte 4 to 7 The function of this bit depends on the configuration of the WRNRD bit as follows Description Value Data b...

Page 1393: ...3 4 5 6 7 8 9 10 11 12 13 14 15 MSK RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset Description Reset Type Name Bit Field Software should not rely on the va...

Page 1394: ...To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x0000 RO reserved 31 16 Mask Extended Identifier Description Value...

Page 1395: ...0 of the ID When using an 11 bit identifier MSK 12 2 are used for bits 10 0 of the ID Description Value The corresponding identifier field ID in the message object cannot inhibit the match in acceptan...

Page 1396: ...RW Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the value of...

Page 1397: ...hould be preserved across a read modify write operation 0x0000 RO reserved 31 16 Message Valid Description Value The message object is ignored by the message handler 0 The message object is configured...

Page 1398: ...a data frame On reception of a remote frame with matching identifier the TXRQST bit of this message object is set if RMTEN 1 1 0 RW DIR 13 Message Identifier This bit field is used with the ID field...

Page 1399: ...ed across a read modify write operation 0x0000 RO reserved 31 16 New Data Description Value No new data has been written into the data portion of this message object by the message handler since the l...

Page 1400: ...changed after a successful reception of a frame 0 The INTPND bit in the CANIFnMCTL register is set after a successful reception of a frame 1 0 RW RXIE 10 Remote Enable Description Value At the recepti...

Page 1401: ...served bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x0 RO reserved 6 4 Data Length Code Description Value Spe...

Page 1402: ...N IFn Data nn CANIFnDnn CAN0 base 0x4004 0000 CAN1 base 0x4004 1000 Offset 0x03C Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO...

Page 1403: ...mission Request n CANTXRQn CAN0 base 0x4004 0000 CAN1 base 0x4004 1000 Offset 0x100 Type RO reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO...

Page 1404: ...x120 Type RO reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 1...

Page 1405: ...CAN Message n Interrupt Pending CANMSGnINT CAN0 base 0x4004 0000 CAN1 base 0x4004 1000 Offset 0x140 Type RO reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO...

Page 1406: ...0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MSGVAL R...

Page 1407: ...Flexible pulse per second output Supports coarse and fine correction methods Multiple addressing modes Four MAC address filters Programmable 64 bit Hash Filter for multicast address filtering Promiscu...

Page 1408: ...N0MDC EN0MDIO TX Pair RX Pair TX RX Controller TX FIFO RX FIFO 20 2 Signal Description The following table lists the external signals of the Ethernet Controller and describes the function of each Some...

Page 1409: ...b modules Clock Control DMA Controller Transmit Receive Controller TX RX Controller Media Access Controller MAC AHB Bus Interface PHY Interface The following sections describe the features and functio...

Page 1410: ...OD register is clear then the transfer resends data in one continuous burst When one transfer is left it is done as a single burst and the transaction is terminated immediately afterward If the RIB bi...

Page 1411: ...uffers However a single descriptor cannot span multiple frames The DMA skips to the next frame buffer when the end of frame is detected Data chaining can be enabled or disabled through the descriptors...

Page 1412: ...y the status fields RDES and TDES of the descriptors The driver has to perform the size calculations The TX DMA transfers the exact number of bytes indicated by buffer size fields of TDES1 to the MAC...

Page 1413: ...rnate descriptors the software should clear the Alternate Descriptor Size ATDS bit in the Ethernet MAC DMA Bus Mode EMACDMABUSMOD register See the section called Enhanced Transmit Descriptor on page 1...

Page 1414: ...ins the address pointer either to the second buffer of the descriptor or the next descriptor TDES6 and TDES7 contain the timestamp Table 20 2 Enhanced Transmit Descriptor 0 TDES0 Description Bit OWN O...

Page 1415: ...ol the insertion of checksums in Ethernet frames that encapsulate TCP UDP or ICMP over IPv4 or IPv6 This field is valid when the First Segment control bit TDES0 28 is set 0x0 Do nothing Checksum Engin...

Page 1416: ...ne detected an IP header error This bit is valid only when TX Checksum Offload is enabled Otherwise it is reserved If the Checksum Offload Engine detects an IP header error it still inserts an IPv4 he...

Page 1417: ...al Check DC bit being enabled in the EMACCFG register 2 UF Underflow Error When set this bit indicates that the MAC aborted the frame because the data arrived late from system memory Underflow Error i...

Page 1418: ...with the least significant 32 bits of the timestamp captured for the corresponding transmit frame This field has the timestamp only if the Last Segment bit LS TDES0 29 in the descriptor is set and Tim...

Page 1419: ...criptor ownership information RDES1 contains the buffer sizes and other bits that control the descriptor chain or ring RDES2 and RDES3 contains the address pointers to the first and second data buffer...

Page 1420: ...il When set this bit indicates that the SA field of frame failed the SA Filter in the MAC 13 LE Length Error When set this bit indicates that the actual length of the frame received and the Length Typ...

Page 1421: ...t this bit indicates that the received frame has a non integer multiple of bytes odd nibbles 2 CE CRC Error When set this bit indicates that a Cyclic Redundancy Check CRC Error occurred on the receive...

Page 1422: ...the next descriptor depending on the value of RCH Bit 14 12 0 Table 20 11 Enhanced Receive Descriptor 2 RDES2 Description Bit Buffer 1 Address Pointer These bits indicate the physical address of Buff...

Page 1423: ...0xA Signaling 0xB to 0xE Reserved 0xF PTP packet with Reserved message type 11 8 IPv6 Packet Received When set this bit indicates that the received packet is an IPv6 packet This bit is updated only w...

Page 1424: ...the corresponding receive frame This field is updated by DMA only for the last descriptor of the receive frame which is indicated by Last Descriptor status bit RDES0 8 31 0 20 3 2 6 DMA Transmission...

Page 1425: ...end of frame buffer The status information is then written to transmit descriptor TDES0 Because the OWN bit is cleared during this step the CPU now owns this descriptor If timestamping was not enable...

Page 1426: ...e descriptor No Y es No Y es No Poll demand A A Start 0 Error Condition OWN bit set Error Condition Error Condition Error Condition TX DMA OSF Mode Operation While in the RUN state the transmit proces...

Page 1427: ...the status with a cleared OWN bit to the corresponding TDES0 thus closing the descriptor If timestamping was not enabled for the previous frame the DMA does not alter the contents of TDES6 and TDES7...

Page 1428: ...oll demand No No A A No pending status and Start 0 Error Condition Error Condition Error Condition Error Condition Error Condition Error Condition OWN Transmit Frame Processing The TX DMA expects that...

Page 1429: ...ro buffer size Transmit Polling Suspended Transmit polling can be suspended by either of the following conditions The DMA detects a descriptor owned by the CPU TDES0 31 0 To resume the driver must giv...

Page 1430: ...the EMACDMAOPMODE register DMA goes to the STOP state otherwise the RX DMA proceeds to Step 8 8 The RX DMA engine checks the last descriptor s OWN bit If the CPU owns the descriptor OWN bit is 0 the R...

Page 1431: ...diate descriptor Frame transfer complete No Flush disabled No Flush the remaining frame Yes Yes No No No Yes Yes Poll demand new frame available No Yes No Own bit set for next desc Flush disabled A A...

Page 1432: ...the frame is transferred to the receive buffer If the frame is contained in a single descriptor both Last Descriptor RDES0 8 and First Descriptor RDES0 9 are set The DMA fetches the next descriptor s...

Page 1433: ...rrupts in the Normal Interrupt group that are enabled in the EMACDMAIM register are ORed together to create the Normal Interrupt Summary NIS bit in the EMACDMARIS register Any of the interrupts in the...

Page 1434: ...ity of triggering the DMA to initiate a burst transfer The DMA also transfers start of frame SOF end of frame EOF CRC and pad insertion information to the TX RX Controller so that this information can...

Page 1435: ...er is transferring data to the MAC the transmission is aborted and the MAC indicates a retry attempt by giving a collision status before the EOF is transferred to the TX RX Controller from the DMA Thi...

Page 1436: ...is present with the receive status it is appended to the frame and received by the MAC and pushed into the TX FIFO before the corresponding receive status word is written Thus two additional location...

Page 1437: ...ined by the size of the RX FIFO 2K and the minimum size of the frame If the frame size if 64 then the asynchronous FIFO depth is 2048 64 32 bytes in length Note that when the status of a partial frame...

Page 1438: ...s the transmit status to the TX RX Controller It then accepts and drops all further data until the next SOF is received The TX RX Controller should retransmit the same frame from SOF on observing a re...

Page 1439: ...flow control is enabled This results in a collision and the remote station backs off If the application requests a frame to be transmitted the frame is scheduled and transmitted even when backpressure...

Page 1440: ...s frame filtering based on the destination source address the application still needs to perform another level of filtering if it decides not to receive any bad frames like runt CRC error frames etc A...

Page 1441: ...res the exact time t2 using its timing reference 3 The master sends a Follow_Up message to the slave which contains t1 information for later use 4 The slave sends a Delay_Req message to the master not...

Page 1442: ...alization the system time counter is written with the value in these registers while for system time correction the offset value is added to or subtracted from the system time In the fine correction m...

Page 1443: ...tten to the Ethernet MAC Time Stamp Addend EMACTIMADD register offset 0x718 to achieve timing synchronization If the MOSC clock source is 25 MHz the frequency division ratio FreqDivisionRatio of the t...

Page 1444: ...ore Sync cycles 20 3 5 2 Transmit Timestamping The MAC captures a timestamp when the Start Frame Delimiter SFD of a frame is sent The transmit frames are marked to indicate whether a timestamp should...

Page 1445: ...because the SSINC field in the EMACSUBSECINC register limits the PTP frequency that can be used to 4 MHz 20 3 5 5 IEEE 1588 2008 Advanced Timestamps In addition to the basic timestamp features mentio...

Page 1446: ...errors because of any frequency offset between the two ports Port 2 returns the Pdelay_Resp message as quickly as possible after the receipt of the Pdelay_Req message The Port 2 returns any one of th...

Page 1447: ...ond PPS0 Output Flexible Pulse Per Second PPS0 Output 80 Bit Timestamp The MAC supports an 80 bit timestamp with a lengthened seconds integer portion which is 48 bits wide The Ethernet MAC System Time...

Page 1448: ...TARGSEC and EMACTARGNANO registers The TRGTBUSY bit in the EMACTARGNANO register indicates when the value is synchronized to the PTP clock domain When this bit is clear a new start time can be program...

Page 1449: ...stination Address DA filtering VLAN Filtering The frame filtering supports a sequence where the packet is not forwarded to VLAN filtering if it does not pass the SA or DA filtering first 20 3 6 1 VLAN...

Page 1450: ...cated in Bit 10 of Receive Descriptor word 0 RDES0 When the RA bit is not set and the VTFE bit in the EMACFRAMEFLTR register is set the frame is dropped if the final VLAN match status is fail In Table...

Page 1451: ...replace the VLAN Type field C VLAN or S VLAN indicated by the CSVL bit of the Ethernet MAC VLAN Tag Inclusion or Replacement EMACVLNINCREP MAC offset 0x584 and the VLAN Tag field in the transmit frame...

Page 1452: ...per recovery Therefore checksum insertion must only be enabled in frames that are less than 2048 PBL 3 4 bytes in size where PBL is the Programmable Burst Length field in the EMACDMABUSMOD register 20...

Page 1453: ...s This engine includes the TCP UDP or ICMPv6 pseudo header bytes for checksum calculation and checks whether the received checksum field matches the calculated value The result of this operation is gi...

Page 1454: ...f the bank then register 1 and so on The Ethernet MAC Remote Wake Up Frame Filter EMACRWUFF register is read the same way The current pointer value of the bank is updated in the Remote Wake Up FIFO Po...

Page 1455: ...with Filter CRC 16 The remote wake up frame is checked only for length error FCS error dribble bit error MII error and collision In addition the remote wake up frame is checked to ensure that it is n...

Page 1456: ...is read the PMT interrupt is cleared in the EMACRIS register at least after four clock cycles of RX clock When software resets the PWRDWN bit in the Ethernet MAC PMT Control and Status EMACPMTCTLSTAT...

Page 1457: ...layer functions needed to transmit and receive data on standard twisted pair cables The PHY directly interfaces to the integrated Media Access Controller MAC The Ethernet PHY uses mixed signal proces...

Page 1458: ...d duplex mode with which to operate If the link partner is unable to auto negotiate the PHY goes into parallel detect mode to determine the speed of the link partner Under parallel detect mode the dup...

Page 1459: ...thout the need for the long Auto Negotiation period 20 4 2 3 Isolate Mode The PHY can be put into Isolate mode by writing ISOLATE bit of the Ethernet PHY Basic Mode Control MR0 EPHYBMCR register addre...

Page 1460: ...ister set MDIO registers 0 to 31 can be performed using the normal direct MDIO access or the indirect method except for the EPHYREGCTL 0x00D and the EPHYADDAR 0x00E which can be accessed only using th...

Page 1461: ...the MII interface is busy When the MIIB bit is 0 the MII interface is available to write to the PHY registers 2 The EMACMIIDATA register should be written with the value to be passed into the EPHYREG...

Page 1462: ...ster address with no increment 9 Initiate write by writing the EMACMIIADDR register fields PLA Physical Layer Address of the PHY The integrated PHY s address is 0x0 MII Address of the PHY register to...

Page 1463: ...he MIIB is clear read the contents of the EMACMIIDATA register Read from Extended PHY Registers The following describes the steps to read from an extended PHY register 1 Check the MIIB bit in the EMAC...

Page 1464: ...unconnected as well Note When entering hibernation in VDD3ON mode the supply rails to the Ethernet resistors R1 R2 R3 R4 found in Figure 20 13 on page 1464 must be switched off 20 5 Initialization an...

Page 1465: ...eceive and Transmit engines then begin processing Receive and Transmit operations The Transmit and Receive processes are independent of each other and can be started or stopped separately 20 5 1 Ether...

Page 1466: ...module by writing 0x0000 0001 to the Ethernet PHY Run Mode Clock Gating Control RCGCEPHY register at offset 0x630 When the R0 bit reads as 1 in the PREPHY register at System Control offset 0xA30 cont...

Page 1467: ...C MII Address EMACMIIADDR register offset 0x010 The PLA value of the EMACMIIADDR register for the internal PHY is 0x00 Table 20 23 Ethernet Register Map See page Description Reset Type Name Offset Eth...

Page 1468: ...Frame Count for Frames Transmitted after Multiple Collisions 0x0000 0000 RO EMACTXCNTMCOL 0x150 1526 Ethernet MAC Transmit Octet Count Good 0x0000 0000 RO EMACTXOCTCNTG 0x164 1527 Ethernet MAC Receive...

Page 1469: ...t Mask Register 0x0000 0000 RW EMACDMAIM 0xC1C 1575 Ethernet MAC Missed Frame and Buffer Overflow Counter 0x0000 0000 RO EMACMFBOC 0xC20 1576 Ethernet MAC Receive Interrupt Watchdog Timer 0x0000 0000...

Page 1470: ...R17 0x0103 RW EPHYSCR 1622 Ethernet PHY MII Interrupt Status 1 MR18 0x0000 RW EPHYMISR1 1625 Ethernet PHY MII Interrupt Status 2 MR19 0x0000 RW EPHYMISR2 1628 Ethernet PHY False Carrier Sense Counter...

Page 1471: ...acement for all transmitted frames Thus for encodings 0x2 0x3 where the most significant bit is 0 the Ethernet MAC Address 0 registers are used For encodings 0x6 0x7 the Ethernet MAC Address 1 registe...

Page 1472: ...the frame to the application Description Value No bytes are removed 0 The last four bytes are removed before forwarding 1 0x0 RW CST 25 Software should not rely on the value of a reserved bit To provi...

Page 1473: ...es 0x5 48 bit times 0x6 40 bit times 0x7 In half duplex mode the minimum IFG can be configured only for 64 bit times IFG 0x4 Lower values are not considered 0x0 RW IFG 19 17 Disable Carrier Sense Duri...

Page 1474: ...the Transmit clock is not looped back internally Description Value MAC does not operate in loopback mode 0 MAC operates in loopback mode 1 0 RW LOOPBM 12 Duplex Mode When this bit is set the MAC oper...

Page 1475: ...with length field greater than or equal to 1 536 bytes are passed to the application without stripping the Pad or FCS field When this bit is cleared the MAC passes all incoming frames without modifyi...

Page 1476: ...When this bit is clear the deferral check function is disabled and the EMAC defers until the CRS signal goes inactive Note This bit is only applicable in half duplex mode Description Value Deferral c...

Page 1477: ...d to the beginning of every Transmit frame The preamble reduction occurs only when the MAC is operating in the full duplex mode Description Value 7 bytes of preamble 0x0 5 bytes of preamble 0x1 3 byte...

Page 1478: ...ved frames irrespective of whether they pass the address filter or not to the application The result of the SA or DA filtering is updated pass or fail in the corresponding bits in the Receive Status W...

Page 1479: ...Word is set When SA Match bit is set and the SA filter fails the MAC drops the frame When this bit is clear the MAC forwards the received frame to the application with the updated SA Match bit of the...

Page 1480: ...eld should be set to 0x1 only when Condition 1 is true that is the MAC is programmed to operate in the full duplex mode and the RFE bit is enabled Otherwise the PAUSE frame filtering may be inconsiste...

Page 1481: ...of received multicast frames according to the hash table 1 0 RW HMC 2 Hash Unicast Description Value MAC performs a perfect destination address filtering for unicast frames It compares the DA field w...

Page 1482: ...of the incoming frame is received as 0x1F52419CB6AF then the internally calculated 6 bit Hash value is 0x2C and Bit 12 of EMACHASHTBLH register is checked for filtering If the DA of the incoming frame...

Page 1483: ...22 23 24 25 26 27 28 29 30 31 HTL RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 HTL RW RW RW RW RW RW RW RW RW RW RW...

Page 1484: ...are available for external PHY addresses Note The integrated PHY s address is 0x00 To access the integrated PHY registers the PLA bits 15 11 must be zeros 0x0 RW PLA 15 11 MII Register These bits sele...

Page 1485: ...re sets this bit to indicate that a read or write access is in progress The EMACMIIDATA register is invalid until this bit is cleared by the MAC Therefore EMACMIIDATA should be kept valid until the MA...

Page 1486: ...e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DATA RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Nam...

Page 1487: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Pause Time This field holds the value to be used in the pause time field in the transmit control frame For example if these bi...

Page 1488: ...lex mode the back pressure feature is disabled 0 In the full duplex mode the MAC enables the flow control operation to transmit pause frames In half duplex mode the MAC enables the back pressure opera...

Page 1489: ...Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write op...

Page 1490: ...when enabled only 12 bits of the VLAN tag in the received frame are used for hash based VLAN filtering 1 0 RW ETV 16 VLAN Tag Identifier for Receive Frames This field contains the 802 1Q VLAN tag to i...

Page 1491: ...ibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x00 RO reserved 31 26 TX RX Controller TX FIFO Full Status Description Value The TX R...

Page 1492: ...his field indicates the state of the MAC Transmit Frame Controller module Description Value IDLE state 0x0 Waiting for status of previous frame or IFG or backoff period to be over 0x1 Generating and t...

Page 1493: ...rame status or timestamp 0x2 Flushing the frame data and status 0x3 0x0 RO RRC 6 5 TX RX Controller RX FIFO Write Controller Active Status Description Value The MTL RX FIFO Write Controller is inactiv...

Page 1494: ...ight sequential writes to this address programs all of the remote wake up frame filter registers Similarly eight sequential reads from the EMACRWUFF register reads all wake up frame registers Ethernet...

Page 1495: ...e of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 RO reserved 30 27 Remote Wake Up FIFO Pointer T...

Page 1496: ...on of a power management event in response to the reception of a wake up frame is enabled 1 0 RW WUPFREN 2 Magic Packet Enable Description Value Magic packet reception does not affect power management...

Page 1497: ...SSOVF bit in the MAC timestamp Status Register EMACTIMSTAT register In this mode this bit is cleared after the completion of the read of this bit In all other modes this bit is reserved Description Va...

Page 1498: ...ceive Interrupt EMACMMCRXRIS register 1 0 RO MMCRX 5 MMC Interrupt Status Description Value Indicates the MMC related Interrupt bits 6 5 in this register are clear 0 Indicates that one or more of the...

Page 1499: ...amp Interrupt Mask Description Value The TSI interrupt status bit in the MAC Raw Interrupt Status EMACRIS register is not masked and can cause an interrupt 0 The assertion of the TIS interrupt status...

Page 1500: ...30 31 reserved AE RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ADDRHI RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW R...

Page 1501: ...W RW RW RW RW RW RW RW RW Type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ADDRLO RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R...

Page 1502: ...RW AE 31 Source Address Description Value When this bit is reset MAC Address1 47 0 is used to compare with the DA fields of the received frame 0 When this bit is set MAC Address1 47 0 is used to comp...

Page 1503: ...ture products the value of a reserved bit should be preserved across a read modify write operation 0x0 RO reserved 23 16 MAC Address1 47 32 This field contains the upper 16 bits 47 32 of the second 6...

Page 1504: ...RW RW RW RW RW RW RW RW RW RW RW Type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ADDRLO RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 1 1 1 1 1 1 1 1 1 1 1 1 1...

Page 1505: ...Address Description Value When this bit is reset the MAC Address2 47 0 is used to compare with the DA fields of the received frame 0 When this bit is set the MAC Address2 47 0 is used to compare with...

Page 1506: ...with future products the value of a reserved bit should be preserved across a read modify write operation 0x0 RO reserved 23 16 MAC Address2 47 32 This field contains the upper 16 bits 47 32 of the t...

Page 1507: ...W RW RW RW RW RW RW Type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ADDRLO RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset D...

Page 1508: ...AE 31 Source Address Description Value When this bit is reset the MAC Address3 47 0 is used to compare with the DA fields of the received frame 0 When this bit is set the MAC Address3 47 0 is used to...

Page 1509: ...ture products the value of a reserved bit should be preserved across a read modify write operation 0x0 RO reserved 23 16 MAC Address3 47 32 This field contains the upper 16 bits 47 32 of the fourth 6...

Page 1510: ...W RW RW RW RW RW RW RW RW RW RW RW RW Type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ADDRLO RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 1 1 1 1 1 1 1 1 1 1 1...

Page 1511: ...atchdog timeout for a received frame is controlled by setting the WD and JE bits in the EMACCFG register 0 When the WD bit of the EMACCFG register is clear the WTO field is used as a watchdog timeout...

Page 1512: ...RO RO RW RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with fut...

Page 1513: ...full or almost half according to the CNTPRSTLVL bit The CNTPRST bit is cleared automatically after 1 clock cycle 1 This bit along with CNTPRSTLVL is useful for debugging and testing the assertion of...

Page 1514: ...aching maximum value the MMC counters do not roll over to zero 1 0 RW CNTSTPRO 1 Counters Reset Description Value No effect 0 All MMC counters are reset This bit is cleared automatically after one clo...

Page 1515: ...reserved UCGF reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 GBF reserved CRCERR ALGNERR reserved RO RO RO RO...

Page 1516: ...or the maximum value 0 The Ethernet MAC Receive Frame Count for CRC Error Frames EMACRXCNTCRCERR register has reached half of the maximum value or the maximum value 1 0x0 RO CRCERR 5 Software should...

Page 1517: ...rved OCTCNT reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved GBF reserved SCOLLGF MCOLLGF RO RO RO RO...

Page 1518: ...Transmitted after Single Collision EMACTXCNTSCOL register has reached half of the maximum value or the maximum value 1 0x0 RO SCOLLGF 14 Software should not rely on the value of a reserved bit To prov...

Page 1519: ...ite operation 0x0 RO reserved 31 18 MMC Receive Unicast Good Frame Counter Interrupt Mask Description Value An interrupt is sent to the interrupt controller when the UCGF bit in the EMACMMCRXRIS regis...

Page 1520: ...across a read modify write operation 0 RO reserved 4 1 MMC Receive Good Bad Frame Counter Interrupt Mask Description Value An interrupt is sent to the interrupt controller when the GBF bit in the EMA...

Page 1521: ...ion 0x0 RO reserved 31 21 MMC Transmit Good Octet Counter Interrupt Mask Description Value An interrupt is sent to the interrupt controller when the OCTCNT bit in the EMACMMCTXRIS register is set 0 Th...

Page 1522: ...Mask Description Value An interrupt is sent to the interrupt controller when the GBF bit in the EMACMMCTXRIS register is set 0 The GBF interrupt is suppressed and not sent to the interrupt controller...

Page 1523: ...Good and Bad Frames EMACTXCNTGB Base 0x400E C000 Offset 0x118 Type RO reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 TXFRMGB RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0...

Page 1524: ...ingle Collision EMACTXCNTSCOL Base 0x400E C000 Offset 0x14C Type RO reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 TXSNGLCOLG RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0...

Page 1525: ...Collisions EMACTXCNTMCOL Base 0x400E C000 Offset 0x150 Type RO reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 TXMULTCOLG RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0...

Page 1526: ...se 0x400E C000 Offset 0x164 Type RO reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 TXOCTG RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset...

Page 1527: ...B Base 0x400E C000 Offset 0x180 Type RO reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RXFRMGB RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R...

Page 1528: ...NTCRCERR Base 0x400E C000 Offset 0x194 Type RO reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RXCRCERR RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 1529: ...LGNERR Base 0x400E C000 Offset 0x198 Type RO reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RXALGNERR RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 1530: ...RXCNTGUNI Base 0x400E C000 Offset 0x1C4 Type RO reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RXUCASTG RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0...

Page 1531: ...0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit s...

Page 1532: ...eplaces VLT in bytes 15 and 16 of all VLAN type transmitted frames Bytes 13 and 14 are 0x8100 0x88a8 0x3 Note Changes to this field take effect only on the start of a frame If you write this register...

Page 1533: ...ained in Step 1 3 Take the upper four bits from the value obtained in Step 2 If the corresponding bit value of the register is 0x1 the frame is accepted Otherwise it is rejected Ethernet MAC VLAN Hash...

Page 1534: ...he value of a reserved bit should be preserved across a read modify write operation 0x0 RO reserved 31 19 Enable MAC address for PTP Frame Filtering Description Value No effect 0 The Destination Addre...

Page 1535: ...TH 11 Enable PTP Packet Processing For Version 2 Format Description Value PTP packets are processed using the IEEE 1588 version 1 format 0 PTP packets are processed using the IEEE 1588 version 2 forma...

Page 1536: ...NO registers This bit is reset after the generation of the Timestamp Trigger Interrupt 1 0x0 RW INTTRIG 4 Timestamp Update This bit should be read zero before updating it This bit is reset when the up...

Page 1537: ...stamp Enable The EMACTIMSEC and the EMACTIMNANO registers must be initialized after enabling this mode On the receive side the MAC processes 1588 frames only if this bit is set Description Value The t...

Page 1538: ...O RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future produc...

Page 1539: ...ds EMACTIMSEC Base 0x400E C000 Offset 0x708 Type RO reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 TSS RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 1540: ...0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TSSS RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Softwa...

Page 1541: ...Update EMACTIMSECU Base 0x400E C000 Offset 0x710 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 TSS RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 0 0 0 0 0 0 0 0 0 0...

Page 1542: ...0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TSSS RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Fie...

Page 1543: ...400E C000 Offset 0x718 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 TSAR RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3...

Page 1544: ...0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TSTR RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Target Ti...

Page 1545: ...usy 0 The Ethernet MAC Target Time Seconds Nanoseconds EMACTARGSEC EMACTARGNANO registers are busy This bit is set when the PPSCTRL field in the EMACPPSCTRL register is programmed to 0x2 or 0x3 and th...

Page 1546: ...RW RW RW RW RW RW RW RW RW RW RW Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with...

Page 1547: ...the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x0 RO reserved 31 2 Timestamp Target Tim...

Page 1548: ...bility with future products the value of a reserved bit should be preserved across a read modify write operation 0x0 RO reserved 31 7 Target Time Register Mode for PPS0 Output This field indicates the...

Page 1549: ...f Three clocks of 50 percent duty cycle and 268 ms period Fourth clock of 195 ms period 134 ms low and 61 ms high This signaling behavior is because of the non linear toggling of bits in the digital r...

Page 1550: ...t 0x0 the binary rollover is 128 Hz and the digital rollover is 64 Hz 0x7 When the PPSEN0 bit 0x1 this encoding is reserved When thePPSEN0 bit 0x0 the binary rollover is 256 Hz and the digital rollove...

Page 1551: ...pe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PPS0INT RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type...

Page 1552: ...5 PPS0WIDTH RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field EN0PPS Output Signal Width These bits store the width betwe...

Page 1553: ...rupted burst until the last word which is a single burst 0x0 During a retry split or loss of bus the DMA rebuilds the pending beats of any burst transfer initiated with a defined fixed burst of 1 4 8...

Page 1554: ...TX DMA uses the PBL bit field as its defined programmable burst length 0x1 0 RW USP 23 RX DMA Programmable Burst Length PBL When the USP bit is 1 this field is used to indicate the maximum number of w...

Page 1555: ...permissible values of 1 2 4 8 16 and 32 Any other value results in undefined behavior When USP is set high this PBL value is applicable only for TX DMA transactions If the number of beats to be transf...

Page 1556: ...ftware Reset The software reset function is driven by this bit The reset operation is completed only when all resets in all active clock domains are deasserted It is essential that all the PHY input c...

Page 1557: ...0x400E C000 Offset 0xC04 Type WO reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 TPD WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2...

Page 1558: ...WO WO WO WO WO WO WO WO WO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RPD WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Re...

Page 1559: ...uses the already existing descriptor address Ethernet MAC Receive Descriptor List Address EMACRXDLADDR Base 0x400E C000 Offset 0xC0C Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29...

Page 1560: ...reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 TXDLADDR RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14...

Page 1561: ...RW1C RW1C RW1C RW1C RW1C RW1C RW1C RW1C RW1C RW1C RW1C RO RO RW1C RW1C RW1C Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a...

Page 1562: ...set This field does not generate an interrupt Description Value Error during RX DMA Write Data Transfer 0x0 reserved 0x1 0x2 Error during TX DMA Read Data Transfer 0x3 Error during RX DMA Descriptor W...

Page 1563: ...al Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in EMACDMAIM register EMACDMARIS register bit 0 Transmit In...

Page 1564: ...eceive Interrupt Description Value No early receive event has occurred 0 The DMA has filled the first data buffer of the packet This bit is cleared when software writes a 1 to this bit or if bit 6 RI...

Page 1565: ...wnership of the descriptor and issue a Receive Poll Demand command If no Receive Poll Demand is issued the receive process resumes when the next recognized incoming frame is received This bit is set o...

Page 1566: ...occurred 0 Indicates the host owns the next descriptor in the transmit list and the DMA cannot acquire it Transmission is suspended The transmit process state bits TS 22 20 explain the transmit proce...

Page 1567: ...e of a reserved bit should be preserved across a read modify write operation 0x0 RO reserved 31 27 Disable Dropping of TCP IP Checksum Error Frames Description Value All error frames are dropped if th...

Page 1568: ...operation has completed 0 The transmit FIFO controller logic is reset to its default values and thus all data in the TX FIFO is lost or flushed This bit is cleared internally when the flushing operati...

Page 1569: ...is in the Suspended state Description Value Transmission process is placed in the stopped state after completing the transmission of the current frame The Next Descriptor position in the Transmit List...

Page 1570: ...n the RX FIFO 1 0x0 RW DGF 5 Receive Threshold Control These two bits control the threshold level of the RX FIFO Transfer request to DMA starts when the frame size within the RX FIFO is larger than th...

Page 1571: ...command is issued before setting EMACRXDLADDR the DMA behavior is unpredictable When this bit is cleared the receive DMA operation is stopped after the transfer of the current frame The next descripto...

Page 1572: ...Field Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x0 RO...

Page 1573: ...e The Receive Watchdog Timeout Interrupt is disabled 0 The Receive Watchdog Timeout Interrupt is enabled Abnormal Interrupt Summary Enable AIE bit 15 must also be set to 0x1 1 0x0 RW RWE 9 Receive Sto...

Page 1574: ...bled Abnormal Interrupt Summary Enable AIE bit 15 must also be set to 0x1 1 0x0 RW TJE 3 Transmit Buffer Unvailable Enable Description Value Transmit Buffer Unavailable Interrupt is disabled 0 Transmi...

Page 1575: ...operation 0x0 RO reserved 31 29 Overflow Bit for FIFO Overflow Counter This bit is set every time the overflow frame counter bits 27 17 overflows that is the RX FIFO overflows with the overflow frame...

Page 1576: ...O RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the...

Page 1577: ...SC RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CURTXDESC RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0...

Page 1578: ...CURRXDESC RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CURRXDESC RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Typ...

Page 1579: ...RTXBUFA RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CURTXBUFA RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type...

Page 1580: ...0 31 CURRXBUFA RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CURRXBUFA RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R...

Page 1581: ...on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x0 RO reserved 31 11 Ethernet MAC Typ...

Page 1582: ...ernal PHY 1 0 RW PHYEXT 31 Ethernet Interface Select This field selects the PHY interface used by the MAC This input is sampled during reset and an update to this register field must result in the MAC...

Page 1583: ...t of the Ethernet PHY Configuration 1 EPHYCFG1 register PHY offset 0x009 0 RW TDRRUN 20 Fast Link Down Mode These bits are sampled on the deassertion of the PHY reset signal and are used as the defaul...

Page 1584: ...Duplex Ability This bit is sampled on the deassertion of the PHY reset signal and is used as the default value for the EXTFD bit of the Ethernet PHY Configuration 2 EPHYCFG2 register PHY offset 0x00A...

Page 1585: ...NEN 0x0 the mode is 100Base TX Half Duplex When ANEN 0x1 the mode is 10Base T Half Duplex 100Base TX Half Duplex 0x2 When ANEN 0x0 the mode is 100Base TX Full Duplex When ANEN 0x1 the mode is 10Base T...

Page 1586: ...erved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 RO reserved 31 19 PTP Clock Reference Enable The PTP cloc...

Page 1587: ...0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 INT reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software...

Page 1588: ...d RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide co...

Page 1589: ...Field Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 RO re...

Page 1590: ...R 0x007 registers When the reset operation is done this bit is cleared to 0 automatically Description Value Normal operation 0 Initiate MII Reset Reset in Process 1 0 RW MIIRESET 15 MII Loopback When...

Page 1591: ...n is initiated whereupon it self clears Operation of the Auto Negotiation process is not affected by the management entity clearing this bit 1 0 RW RESTARTAN 9 Duplex Mode When auto negotiation is dis...

Page 1592: ...tion Value Device does not support 100Base TX in full duplex mode 0 Device supports 100Base TX in full duplex mode 1 1 RO 100BTXFD 14 100Base TX Half Duplex Capable Description Value The device does n...

Page 1593: ...tion detected cleared on read or by reset Fault criteria Far End Fault Indication or notification from Link Partner of Remote Fault 1 0 RO RFAULT 4 Auto Negotiation Enabled Description Value Device is...

Page 1594: ...pe Name Bit Field Extended Capability Enable Description Value Basic register set capabilities only 0 Extended register capabilities 1 1 RO EXTEN 0 June 18 2014 1594 Texas Instruments Production Data...

Page 1595: ...HYID1 and EPHYID2 register The most significant OUI field OUIMSB in the EPHYID1 register is equal to 0x0002 the two most significant bits of the OUI are ignored The least significant OUI field OUILSB...

Page 1596: ...gnored The least significant OUI field OUILSB in the EPHYID2 register is equal to 0x28 Ethernet PHY Identifier Register 2 MR3 EPHYID2 Base n a Address 0x003 Type R reset 0xA221 0 1 2 3 4 5 6 7 8 9 10...

Page 1597: ...be preserved across a read modify write operation 0 RO reserved 14 Remote Fault Description Value No Remote Fault detected 0 Advertises that this device has detected a Remote Fault 1 0 RW RF 13 Softw...

Page 1598: ...ported by the internal PHY 1 0 RO 100BT4 9 100Base TX Full Duplex Support Description Value 100Base TX Full Duplex not supported by the internal PHY 0 100Base TX Full Duplex is supported by the intern...

Page 1599: ...0 RO NP 15 Acknowledge Description Value Not acknowledged The Auto Negotiation state machine will automatically control the this bit based on the incoming FLP bursts 0 Link Partner acknowledges recept...

Page 1600: ...ption Value 100Base TX is not supported by the Link Partner 0 100Base TX is supported by the Link Partner 1 0 RO 100BTX 7 10Base T Full Duplex Support Description Value 10Base T Full Duplex is not sup...

Page 1601: ...ault Description Value A fault has not been detected 0 A fault has been detected via the Parallel Detection function 1 0 RO PDF 4 Link Partner Next Page Able Description Value Link Partner does not su...

Page 1602: ...on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x0 RO reserved 14 Message Page Descri...

Page 1603: ...nterpreted as a Message Page as defined in annex 28C of IEEE 802 3u Otherwise the code is interpreted as an Unformatted Page and the interpretation is application specific The default value of the COD...

Page 1604: ...ge transfer desired 0 Another next page desired 1 0 RO NP 15 Acknowledge The auto negotiation state machine automatically controls this bit based on the incoming fast link pulse FLP bursts Software sh...

Page 1605: ...ggle bit in previously transmitted Link Code Word was 0 1 0 RO TOG 11 Code This field represents the code field of the next page transmission If the MP bit is set bit 13 of this RW register then the c...

Page 1606: ...PHYHOLD mode set in the EMACPC register and wake up the EPHY Description Value Configuration process is not complete 0 Configuration process is complete and the PHY can continue and complete its inte...

Page 1607: ...k Description Value Normal Auto MDI MDIX mode 0 Enable Robust Auto MDI MDIX resolution 1 0 RW RAMDIX 5 Fast Auto Negotiation Enable Adjusting these bits reduces the time it takes to auto negotiate bet...

Page 1608: ...l Inhibit Timer 75 ms Auto Negate Wait Timer 50 ms 0x1 Break Link Timer 240 ms Link Fail Inhibit Timer 150 ms Auto Negate Wait Timer 100 ms 0x2 reserved 0x3 0 RW FANSEL 3 2 FAST RXDV Detection Enablin...

Page 1609: ...bit should be preserved across a read modify write operation 0x0 RO reserved 15 7 Fast Link Up in Parallel Detect Mode In fast auto MDI X and in robust auto MDI X modes bits 6 and 5 in register EPHYC...

Page 1610: ...f Transmit Error Description Value Enable detection of deassertion of the internal transmit enable on an odd nibble boundary In this case the internal transmit enable is extended by one additional tra...

Page 1611: ...provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x0 RO reserved 15 8 Polarity Swap Description Value MDI pairs normal R...

Page 1612: ...in a 10 s interval is reached the link is dropped Bit 2 Drop the link based on MLT3 Errors count Violation of the MLT3 coding in the DSP output When a predefined number of 20 MLT3 Error occurrences i...

Page 1613: ...nly the value in the address register is incremented For read accesses the value of the address register remains unchanged This register is the MDIO Manageable Device MMD access control In general reg...

Page 1614: ...cesses of EPHYADDAR register 0x00E to the appropriate MMD The PHY uses the vendor specific DEVAD 4 0 0x1F for accesses All accesses through registers EPHYREGCR and EPHYADDAR should use this DEVAD Tran...

Page 1615: ...O reset 0x0000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ADDRDATA WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Address o...

Page 1616: ...it is affected by the settings of the MDIXEN and FORCEMDIX bits in the EPHYCTL register When MDIX is enabled but not forced this bit updates dynamically as the Auto MDIX algorithm swaps between MDI an...

Page 1617: ...ived Description Value Link Code Word Page has not been received 0 A new Link Code Word Page has been received This is a duplicate of Page Received bit 1 in the EPHYANER register and it is cleared on...

Page 1618: ...ion or Forced Modes Therefore it is only valid if Auto Negotiation is enabled and complete and there is a valid link or if Auto Negotiation is disabled and there is a valid link 0 RO DUPLEX 2 Speed St...

Page 1619: ...ving Modes Enable Description Value Normal mode of operation 0 Enable power saving modes 1 0 RW PSEN 14 Power Saving Modes Description Value Normal Normal operation mode PHY is fully functional 0x0 IE...

Page 1620: ...ue of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 RO reserved 7 5 Collision in Full Duplex Mode...

Page 1621: ...ndent on the event enables in the EPHYMISR register 0x012 1 RW INTEN 1 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit...

Page 1622: ...should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 RO reserved 15 14 Ch...

Page 1623: ...bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 RO reserved 7 6 Link Status Interrupt Enable Description Value...

Page 1624: ...Enable interrupt on False Carrier Counter Register half full event 1 0 RW FCHFEN 1 Receive Error Counter Register Half Full Event Interrupt Description Value Receive Error Counter Register half full...

Page 1625: ...set Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a...

Page 1626: ...on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 RO reserved 7 Auto Negotiation Error...

Page 1627: ...ption Value Sleep mode interrupt disabled 0 Sleep Mode event interrupt enabled 1 0 RW SLEEPEN 2 Polarity Changed Interrupt Enable Description Value Polarity Change interrupt is disabled 0 Polarity cha...

Page 1628: ...O RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the va...

Page 1629: ...RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Receive Error Count When a valid carrier is present while EN0RXDV is active and there is at least one...

Page 1630: ...should be preserved across a read modify write operation 0 RO reserved 15 PRBS Single Continuous Mode Description Value Single mode selected When BIST Error Counter reaches its max value the PRBS chec...

Page 1631: ...served bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 RO reserved 7 Transmit Data in MII Loopback Mode Descrip...

Page 1632: ...0x00 Near end loopback PCS Input Loopback 0x01 Near end loopback PCS Output Loopback In 100Base TX only 0x02 reserved 0x03 Near end loopback Digital Loopback 0x04 reserved 0x05 0x07 Near end loopback...

Page 1633: ...re should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 RO reserved 15 11...

Page 1634: ...TPTD pair Transmit on TPRD pair 1 0 RW FORCEMDI 14 Pause Receive Negotiated Status Description Value No effect 0 Indicates that pause receive should be enabled in the MAC This bit is set based on bits...

Page 1635: ...eserved bit should be preserved across a read modify write operation 0 RO reserved 10 8 Bypass LED Stretching This bypasses LED stretching and allows the LEDs to reflect normal operation values Descri...

Page 1636: ...T lower receiver threshold to allow operation with longer cables 1 0 RW RXTHEN 13 Squelch Configuration Used to set the Peak Squelch ON threshold for the 10Base T receiver Every value corresponds to...

Page 1637: ...detected 0 Inverted Polarity detected 1 0 RO POLSTAT 4 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be pres...

Page 1638: ...0 0 0 0 0 Reset Description Reset Type Name Bit Field BIST Error Count This field holds the number of erroneous bytes that were received by the PRBS checker The value in this register is locked when a...

Page 1639: ...RO RO RO Type 0 1 1 1 0 1 1 1 1 0 1 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the valu...

Page 1640: ...products the value of a reserved bit should be preserved across a read modify write operation 0 RO reserved 14 10 Link Quality Indication The value of these bits are valid only when link is active wh...

Page 1641: ...rmal Operation 0 Soft reset This mode resets the digital portion of the PHY and all of the registers This bit self clears after completion 1 0 RW SWRST 15 Software Restart Description Value Normal Ope...

Page 1642: ...d across a read modify write operation 0 RO reserved 15 12 LED2 Configuration The following encodings are used to program the specific function desired for the LED Description Value Link OK 0x0 RX TX...

Page 1643: ...on desired for the LED Description Value Link OK 0x0 RX TX Activity 0x1 TX Activity 0x2 RX Activity 0x3 Collision 0x4 100 Base TX 0x5 10 Base TX 0x6 Full Duplex 0x7 Link OK Blink on TX RX Activity 0x8...

Page 1644: ...isconnect allows flexibility during USB device start up The controller complies with OTG Standard s Session Request Protocol SRP and Host Negotiation Protocol HNP The TM4C1294NCPDT USB module has the...

Page 1645: ...ort pin The USB0VBUS and USB0ID signals are configured by clearing the appropriate DEN bit in the GPIO Digital Enable GPIODEN register For more information on configuring GPIOs see General Purpose Inp...

Page 1646: ...in Host mode to control an external power source to supply power to the USB bus TTL O PA6 5 PA7 11 PD6 5 40 41 127 USB0EPEN This signal senses the state of the USB ID signal The USB PHY enables an int...

Page 1647: ...nfiguration USBCCONF 0x061 USB Transmit Dynamic FIFO Sizing USBTXFIFOSZ 0x062 USB Receive Dynamic FIFO Sizing USBRXFIFOSZ 0x063 USB Transmit FIFO Start Address USBTXFIFOADD 0x064 USB Receive FIFO Star...

Page 1648: ...Endpoint 4 USBTXHUBPORT4 0x0A3 USB Receive Functional Address Endpoint 4 USBRXFUNCADDR4 0x0A4 USB Receive Hub Address Endpoint 4 USBRXHUBADDR4 0x0A6 USB Receive Hub Port Endpoint 4 USBRXHUBPORT4 0x0A7...

Page 1649: ...ive Control and Status Endpoint 2 High USBRXCSRH2 0x127 USB Receive Byte Count Endpoint 2 USBRXCOUNT2 0x128 USB Host Transmit Configure Type Endpoint 2 USBTXTYPE2 0x12A USB Host Transmit Interval Endp...

Page 1650: ...62 USB Transmit Control and Status Endpoint 6 High USBTXCSRH6 0x163 USB Maximum Receive Data Endpoint 6 USBRXMAXP6 0x164 USB Receive Control and Status Endpoint 6 Low USBRXCSRL6 0x166 USB Receive Cont...

Page 1651: ...t Count in Block Transfer Endpoint 2 USBRQPKTCOUNT2 0x308 USB Request Packet Count in Block Transfer Endpoint 3 USBRQPKTCOUNT3 0x30C USB Request Packet Count in Block Transfer Endpoint 4 USBRQPKTCOUNT...

Page 1652: ...DRISC 0x418 USB General Purpose Control and Status USBGPCS 0x41C USB VBUS Droop Control USBVDC 0x430 USB VBUS Droop Control Raw Interrupt Status USBVDCRIS 0x434 USB VBUS Droop Control Interrupt Mask U...

Page 1653: ...e in the ADC The interrupt generation and ADC triggering logic is separate and independent This flexibility means for example that an interrupt can be generated on a rising edge and the ADC triggered...

Page 1654: ...he function of each The Analog Comparator output signals are alternate functions for some GPIO signals and default to be GPIO signals at reset The column in the table below titled Pin Mux Pin Assignme...

Page 1655: ...input Cn input sources for VIN can be the C0 or an internal reference VIREF Figure 22 2 Structure of Comparator Unit ACCTL CINV TrigGen output ACSTAT IntGen 1 0 2 reference input ve input alternate ve...

Page 1656: ...de In each range the internal reference VIREF has 16 preprogrammed thresholds or step values The threshold to be used to compare the external input voltage against is selected using the VREF field in...

Page 1657: ...minimum and maximum values for each threshold step depending on process and temperature The minimum and maximum values for each step are given by VIREF VREF Min Ideal VIREF VREF Ideal Step size 2 mV...

Page 1658: ...397 2 Enable the clock to the appropriate GPIO modules via the RCGCGPIO register see page 382 To find out which GPIO ports to enable refer to Table 26 5 on page 1808 3 In the GPIO module enable the GP...

Page 1659: ...rupt Status 0x0000 0000 RO ACRIS 0x004 1662 Analog Comparator Interrupt Enable 0x0000 0000 RW ACINTEN 0x008 1663 Analog Comparator Reference Voltage Control 0x0000 0000 RW ACREFCTL 0x010 1664 Analog C...

Page 1660: ...iption Value No interrupt has occurred or the interrupt is masked 0 The IN2 bits in the ACRIS register and the ACINTEN registers are set providing an interrupt to the interrupt controller 1 This bit i...

Page 1661: ...eserved bit should be preserved across a read modify write operation 0x0000 000 RO reserved 31 3 Comparator 2 Interrupt Status Description Value An interrupt has not occurred 0 Comparator 2 has genera...

Page 1662: ...To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x00 RO reserved 31 3 Comparator 2 Interrupt Enable Description Valu...

Page 1663: ...adder Enable Description Value The resistor ladder is unpowered 0 Powers on the resistor ladder The resistor ladder is connected to VDDA 1 This bit is cleared at reset so that the internal reference c...

Page 1664: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bi...

Page 1665: ...ucts the value of a reserved bit should be preserved across a read modify write operation 0x0000 0 RO reserved 31 12 Trigger Output Enable Description Value ADC events are suppressed and not sent to t...

Page 1666: ...e ISEN field specifies the sense of the comparator output that generates an interrupt The sense conditioning is as follows Description Value Level sense see ISLVAL 0x0 Falling edge 0x1 Rising edge 0x2...

Page 1667: ...ure products the value of a reserved bit should be preserved across a read modify write operation 0x0 RO reserved 31 19 Comparator Output 2 Present Description Value Comparator output 2 is not present...

Page 1668: ...ription Value Comparator 1 is not present 0 Comparator 1 is present 1 0x1 RO CMP1 1 Comparator 0 Present Description Value Comparator 0 is not present 0 Comparator 0 is present 1 0x1 RO CMP0 0 June 18...

Page 1669: ...ides a great deal of flexibility and can generate simple PWM signals such as those required by a simple charge pump as well as paired PWM signals with dead band delays such as those required by a half...

Page 1670: ...PWM generator blocks Extended PWM synchronization of timer comparator updates across the PWM generator blocks Interrupt status summary of the PWM generator blocks Extended PWM fault handling with mul...

Page 1671: ...TL Control and Status PWMSYNC PWMSTATUS PWMPP Figure 23 2 PWM Generator Block Diagram PWMnCMPA Comparators PWMnCMPB PWMnLOAD Timer PWMnCOUNT PWMnDBCTL Dead Band Generator PWMnDBRISE PWMnDBFALL PWMnCTL...

Page 1672: ...nerator 0 TTL O PF0 6 42 M0PWM0 Motion Control Module 0 PWM 1 This signal is controlled by Module 0 PWM Generator 0 TTL O PF1 6 43 M0PWM1 Motion Control Module 0 PWM 2 This signal is controlled by Mod...

Page 1673: ...ounting up and when counting down and thus are qualified by the counter direction signal These qualified pulses are used in the PWM generation process If either comparator match value is greater than...

Page 1674: ...ey coincide with the zero or load events If the match A and match B events coincide the first signal pwmA is generated based only on the match A event and the second signal pwmB is generated based onl...

Page 1675: ...ge of the pwmB signal The resulting signals are a pair of active High signals where one is always High except for a programmable amount of time at transitions where both are Low These signals are ther...

Page 1676: ...g register contents in one of the following three ways Immediately The write value has immediate effect and the hardware reacts immediately Locally Synchronized The write value does not affect the log...

Page 1677: ...d with circuits that generate an active High or active Low signal to indicate an error condition A MnFAULTn pins may be individually programmed for the appropriate logic sense using the PWMnFLTSEN reg...

Page 1678: ...al is 0 not 1 as specified in the PWMFAULTVAL register 23 4 Initialization and Configuration The following example shows how to initialize PWM Generator 0 with a 25 kHz frequency a 25 duty cycle on th...

Page 1679: ...ock is enabled before any PWM module registers are accessed Table 23 2 PWM Register Map See page Description Reset Type Name Offset 1683 PWM Master Control 0x0000 0000 RW PWMCTL 0x000 1685 PWM Time Ba...

Page 1680: ...ger Enable 0x0000 0000 RW PWM1INTEN 0x084 1716 PWM1 Raw Interrupt Status 0x0000 0000 RO PWM1RIS 0x088 1718 PWM1 Interrupt Status and Clear 0x0000 0000 RW1C PWM1ISC 0x08C 1720 PWM1 Load 0x0000 0000 RW...

Page 1681: ...Enable 0x0000 0000 RW PWM3INTEN 0x104 1716 PWM3 Raw Interrupt Status 0x0000 0000 RO PWM3RIS 0x108 1718 PWM3 Interrupt Status and Clear 0x0000 0000 RW1C PWM3ISC 0x10C 1720 PWM3 Load 0x0000 0000 RW PWM3...

Page 1682: ...TAT0 0x904 1742 PWM2 Fault Status 1 0x0000 0000 PWM2FLTSTAT1 0x908 1739 PWM3 Fault Pin Logic Sense 0x0000 0000 RW PWM3FLTSEN 0x980 1740 PWM3 Fault Status 0 0x0000 0000 PWM3FLTSTAT0 0x984 1742 PWM3 Fau...

Page 1683: ...ide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x0000 RO reserved 31 4 Update PWM Generator 3 Description Value No effect 0...

Page 1684: ...the updates have completed it cannot be cleared by software 0 RW GLOBALSYNC1 1 Update PWM Generator 0 Description Value No effect 0 Any queued update to a load or comparator register in PWM generator...

Page 1685: ...15 SYNC0 SYNC1 SYNC2 SYNC3 reserved RW RW RW RW RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the val...

Page 1686: ...4002 8000 Offset 0x008 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1...

Page 1687: ...3 MnPWM2 Output Enable Description Value The MnPWM2 signal has a zero value 0 The generated pwm1A signal is passed to the MnPWM2 pin 1 0 RW PWM2EN 2 MnPWM1 Output Enable Description Value The MnPWM1 s...

Page 1688: ...t 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PWM0INV PWM1INV PWM2INV PWM3INV PWM4INV PWM5INV PWM6INV PWM7INV reserved RW RW RW RW RW RW RW RW RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Re...

Page 1689: ...WM2 signal is not inverted 0 The MnPWM2 signal is inverted 1 0 RW PWM2INV 2 Invert MnPWM1 Signal Description Value The MnPWM1 signal is not inverted 0 The MnPWM1 signal is inverted 1 0 RW PWM1INV 1 In...

Page 1690: ...RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FAULT0 FAULT1 FAULT2 FAULT3 FAULT4 FAULT5 FAULT6 FAULT7 reserved RW RW RW RW RW RW...

Page 1691: ...lue The generated pwm1A signal is passed to the MnPWM2 pin 0 The MnPWM2 output signal is driven to the value specified by the PWM2 bit in the PWMFAULTVAL register 1 0 RW FAULT2 2 MnPWM1 Fault Descript...

Page 1692: ...ftware should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x000 RO reserv...

Page 1693: ...the PWM generator 3 block asserts an interrupt 1 0 RW INTPWM3 3 PWM2 Interrupt Enable Description Value The PWM generator 2 interrupt is suppressed and not sent to the interrupt controller 0 An inter...

Page 1694: ...1 INTPWM2 INTPWM3 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a r...

Page 1695: ...e of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x000 RO reserved 15 4 PWM3 Interrupt Asserted De...

Page 1696: ...rupt has not been asserted 0 The PWM generator 0 block interrupt is asserted 1 The PWM0RIS register shows the source of this interrupt This bit is cleared by writing a 1 to the corresponding bit in th...

Page 1697: ...13 14 15 INTPWM0 INTPWM1 INTPWM2 INTPWM3 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not r...

Page 1698: ...15 4 PWM3 Interrupt Status Description Value The PWM generator 3 block interrupt is not asserted or is not enabled 0 An enabled interrupt for the PWM generator 3 block is asserted 1 The PWM3RIS regist...

Page 1699: ...d or is not enabled 0 An enabled interrupt for the PWM generator 0 block is asserted 1 The PWM0RIS register shows the source of this interrupt This bit is cleared by writing a 1 to the corresponding b...

Page 1700: ...ved 31 4 Generator 3 Fault Status Description Value The fault condition for PWM generator 3 is not asserted 0 The fault condition for PWM generator 3 is asserted If the FLTSRC bit in the PWM3CTL regis...

Page 1701: ...generator 0 is not asserted 0 The fault condition for PWM generator 0 is asserted If the FLTSRC bit in the PWM0CTL register is clear the input is the source of the fault condition and is therefore ass...

Page 1702: ...bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x0000 00 RO reserved 31 8 MnPWM7 Fault Value Description Value...

Page 1703: ...driven Low during fault conditions if the FAULT2 bit in the PWMFAULT register is set 0 The MnPWM2 output signal is driven High during fault conditions if the FAULT2 bit in the PWMFAULT register is se...

Page 1704: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved...

Page 1705: ...PWM5EN bit in the PWMENABLE register are used by the PWM generator the next time the counter is 0 0x2 Globally Synchronized Writes to the PWM5EN bit in the PWMENABLE register are used by the PWM gene...

Page 1706: ...the PWM2EN bit in the PWMENABLE register are used by the PWM generator the next time the counter is 0 0x2 Globally Synchronized Writes to the PWM2EN bit in the PWMENABLE register are used by the PWM...

Page 1707: ...PWM0EN bit in the PWMENABLE register are used by the PWM generator the next time the counter is 0 0x2 Globally Synchronized Writes to the PWM0EN bit in the PWMENABLE register are used by the PWM gene...

Page 1708: ...O RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ENABLE MODE DEBUG LOADUPD CMPAUPD CMPBUPD GENAUPD GENBUPD DBCTLUPD DBRISEUPD DBFALLUPD...

Page 1709: ...ed by software and negates the utility of the extend feature It applies to all fault condition sources as specified in the FLTSRC field Description Value The FAULT input deassertion is unaffected 0 Th...

Page 1710: ...lly Synchronized Updates to the register are reflected to the generator the next time the counter is 0 0x2 Globally Synchronized Updates to the register are delayed until the next time the counter is...

Page 1711: ...ext time the counter is 0 after a synchronous update has been requested through the PWMCTL register 1 0 RW CMPBUPD 5 Comparator A Update Mode Description Value Locally Synchronized Updates to the PWMn...

Page 1712: ...o the load value back down to 0 and then repeats Count Up Down mode 1 0 RW MODE 1 PWM Block Enable Note Disabling the PWM by clearing the ENABLE bit does not clear the COUNT field of the PWMnCOUNT reg...

Page 1713: ...ed an ADC trigger if more than one is specified The PWMnRIS register provides information about which events have caused raw interrupts PWMn Interrupt and Trigger Enable PWMnINTEN PWM0 base 0x4002 800...

Page 1714: ...alue while counting up 1 0 RW TRCMPAU 10 Trigger for Counter PWMnLOAD Description Value No ADC trigger is output 0 An ADC trigger pulse is output when the counter matches the PWMnLOAD register 1 0 RW...

Page 1715: ...g down 1 0 RW INTCMPAD 3 Interrupt for Counter PWMnCMPA Up Description Value No interrupt 0 A raw interrupt occurs when the counter matches the value in the PWMnCMPA register value while counting up 1...

Page 1716: ...0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 INTCNTZERO INTCNTLOAD INTCMPAU INTCMPAD INTCMPBU INTCMPBD reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0...

Page 1717: ...e counting up 1 This bit is cleared by writing a 1 to the INTCMPAU bit in the PWMnISC register 0 RO INTCMPAU 2 Counter Load Interrupt Status Description Value An interrupt has not occurred 0 The count...

Page 1718: ...O RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 INTCNTZERO INTCNTLOAD INTCMPAU INTCMPAD INTCMPBU INTCMPBD reserved RW1C RW1C RW1C RW1C RW1C RW1C RO RO RO RO...

Page 1719: ...bit also clears the INTCMPAU bit in the PWMnRIS register 0 RW1C INTCMPAU 2 Counter Load Interrupt Description Value No interrupt has occurred or the interrupt is masked 0 The INTCNTLOAD bits in the PW...

Page 1720: ...xt time the counter reaches zero If the update mode is globally synchronized it is used the next time the counter reaches zero after a synchronous update has been requested through the PWM Master Cont...

Page 1721: ...eld should be cleared by resetting the PWM registers through the SRPWM register in the System Control Module PWMn Counter PWMnCOUNT PWM0 base 0x4002 8000 Offset 0x054 Type RO reset 0x0000 0000 16 17 1...

Page 1722: ...lobally synchronized it is used the next time the counter reaches zero after a synchronous update has been requested through the PWM Master Control PWMCTL register see page 1683 If this register is re...

Page 1723: ...ized it is used the next time the counter reaches zero after a synchronous update has been requested through the PWM Master Control PWMCTL register see page 1683 If this register is rewritten before t...

Page 1724: ...is immediate based on the GENAUPD field encoding in the PWMnCTL register the ACTCMPBD ACTCMPBU ACTCMPAD ACTCMPAU ACTLOAD and ACTZERO values are used immediately If the update mode is locally synchron...

Page 1725: ...0 Invert pwmA 0x1 Drive pwmA Low 0x2 Drive pwmA High 0x3 0x0 RW ACTCMPBU 9 8 Action for Comparator A Down This field specifies the action to be taken when the counter matches comparator A while counti...

Page 1726: ...ion Value Do nothing 0x0 Invert pwmA 0x1 Drive pwmA Low 0x2 Drive pwmA High 0x3 0x0 RW ACTLOAD 3 2 Action for Counter 0 This field specifies the action to be taken when the counter is zero Description...

Page 1727: ...te based on the GENBUPD field encoding in the PWMnCTL register the ACTCMPBD ACTCMPBU ACTCMPAD ACTCMPAU ACTLOAD and ACTZERO values are used immediately If the update mode is locally synchronized these...

Page 1728: ...g 0x0 Invert pwmB 0x1 Drive pwmB Low 0x2 Drive pwmB High 0x3 0x0 RW ACTCMPBU 9 8 Action for Comparator A Down This field specifies the action to be taken when the counter matches comparator A while co...

Page 1729: ...nothing 0x0 Invert pwmB 0x1 Drive pwmB Low 0x2 Drive pwmB High 0x3 0x0 RW ACTLOAD 3 2 Action for Counter 0 This field specifies the action to be taken when the counter is 0 Description Value Do nothin...

Page 1730: ...n the PWMnCTL register the ENABLE bit value is used immediately If the update mode is locally synchronized this value is used the next time the counter reaches zero If the update mode is globally sync...

Page 1731: ...xt time the counter reaches zero If the update mode is globally synchronized this value is used the next time the counter reaches zero after a synchronous update has been requested through the PWM Mas...

Page 1732: ...ed the next time the counter reaches zero If the update mode is globally synchronized this value is used the next time the counter reaches zero after a synchronous update has been requested through th...

Page 1733: ...ed PWMn Fault Source 0 PWMnFLTSRC0 PWM0 base 0x4002 8000 Offset 0x074 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO...

Page 1734: ...ondition 0 The Fault1 signal value is ORed with all other fault condition generation inputs Faultn signals and digital comparators 1 Note The FLTSRC bit in the PWMnCTL register must be set for this bi...

Page 1735: ...Mn Fault Source 1 PWMnFLTSRC1 PWM0 base 0x4002 8000 Offset 0x078 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type...

Page 1736: ...ster must be set for this bit to affect fault condition generation 0 RW DCMP5 5 Digital Comparator 4 Description Value The trigger from digital comparator 4 is suppressed and cannot generate a fault c...

Page 1737: ...t condition 0 The trigger from digital comparator 1 is ORed with all other fault condition generation inputs Faultn signals and digital comparators 1 Note The FLTSRC bit in the PWMnCTL register must b...

Page 1738: ...e fault condition asserts with respect to the PWM clock The counter decrements at the PWM clock rate without pause or condition PWMn Minimum Fault Period PWMnMINFLTPER PWM0 base 0x4002 8000 Offset 0x0...

Page 1739: ...Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify wr...

Page 1740: ...for that particular generator PWMn Fault Status 0 PWMnFLTSTAT0 PWM0 base 0x4002 8000 Offset 0x804 Type reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO...

Page 1741: ...bit is set this bit is RW1C and represents a sticky version of the MnFAULT1 input signal after the logic sense adjustment If FAULT1 is set the input transitioned to the active state previously If FAUL...

Page 1742: ...d for that particular generator PWMn Fault Status 1 PWMnFLTSTAT1 PWM0 base 0x4002 8000 Offset 0x808 Type reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO...

Page 1743: ...s cleared The DCMP5 bit is cleared by writing it with the value 1 0 DCMP5 5 Digital Comparator 4 Trigger If the PWMnCTL register LATCH bit is clear this bit represents the current state of the Digital...

Page 1744: ...TL register LATCH bit is set this bit represents a sticky version of the trigger If DCMP1 is set the trigger transitioned to the active state previously If DCMP1 is clear the trigger has not transitio...

Page 1745: ...value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x0 RO reserved 31 11 One Shot Mode Descript...

Page 1746: ...ue No generators 0x0 1 generator 0x1 2 generators 0x2 3 generators 0x3 4 generators 0x4 reserved 0x5 0xF The number of PWM outputs is 2 times the number of PWM generators 0x4 RO GCNT 3 0 June 18 2014...

Page 1747: ...bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x0000 0000 RO reserved 31 9 Use PWM Clock Divisor Description V...

Page 1748: ...apture using built in timer The input frequency of the QEI inputs may be as high as 1 4 of the processor frequency for example 12 5 MHz for a 50 MHz system Interrupt generation on Index pulse Velocity...

Page 1749: ...POS Velocity Accumulator QEICOUNT QEISPEED Velocity Timer QEILOAD QEITIME PhA PhB IDX clk dir Interrupt Control Status QEICTL QEISTAT Figure 24 2 on page 1750 shows the logic that is provided to allow...

Page 1750: ...pecified GPIO port pin For more information on configuring GPIOs see General Purpose Input Outputs GPIOs on page 742 Table 24 1 QEI Signals 128TQFP Description Buffer Type Pin Type Pin Mux Pin Assignm...

Page 1751: ...er is automatically reset on one of two conditions sensing the index pulse or reaching the maximum position value The reset mode is determined by the RESMODE bit of the QEICTL register When RESMODE is...

Page 1752: ...rns 10 times per second If the timer were clocked at 10 000 Hz and the load value was 2 500 of a second it would count 20 480 pulses per update Using the above equation rpm 10000 1 20480 60 2500 2048...

Page 1753: ...ble 26 5 on page 1808 5 Configure the quadrature encoder to capture edges on both signals and maintain an absolute position by resetting on index pulses A 1000 line encoder with four edges per line re...

Page 1754: ...aximum Position 0x0000 0000 RW QEIMAXPOS 0x00C 1761 QEI Timer Load 0x0000 0000 RW QEILOAD 0x010 1762 QEI Timer 0x0000 0000 RO QEITIME 0x014 1763 QEI Velocity Counter 0x0000 0000 RO QEICOUNT 0x018 1764...

Page 1755: ...of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x000 RO reserved 31 20 Input Filter Prescale Coun...

Page 1756: ...efore being applied to the QEICOUNT accumulator Predivider Value 1 0x0 2 0x1 4 0x2 8 0x3 16 0x4 32 0x5 64 0x6 128 0x7 0x0 RW VELDIV 8 6 Capture Velocity Description Value No effect 0 Enables capture o...

Page 1757: ...internal PhB input operates as the direction DIR signal 1 0 RW SIGMODE 2 Swap Signals Note if the INVA or INVB bit are set the inversion of the signals occur prior to the swap Description Value No eff...

Page 1758: ...0 0 0 Reset Description Reset Type Name Bit Field Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved...

Page 1759: ...8 19 20 21 22 23 24 25 26 27 28 29 30 31 POSITION RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 POSITION RW RW RW RW...

Page 1760: ...2 C000 Offset 0x00C Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 MAXPOS RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3...

Page 1761: ...QEI Timer Load QEILOAD QEI0 base 0x4002 C000 Offset 0x010 Type RW reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 LOAD RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Type 0 0 0 0 0...

Page 1762: ...21 22 23 24 25 26 27 28 29 30 31 TIME RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TIME RO RO RO RO RO RO RO RO RO...

Page 1763: ...egister is provided for information purposes only This counter does not increment when the VELEN bit in the QEICTL register is clear QEI Velocity Counter QEICOUNT QEI0 base 0x4002 C000 Offset 0x018 Ty...

Page 1764: ...02 C000 Offset 0x01C Type RO reset 0x0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SPEED RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3...

Page 1765: ...ross a read modify write operation 0x0000 000 RO reserved 31 4 Phase Error Interrupt Enable Note The INTERROR bit is only applicable when the QEI is operating in quadrature phase mode SIGMODE 0 and sh...

Page 1766: ...alue The INTINDEX interrupt is suppressed and not sent to the interrupt controller 0 An interrupt is sent to the interrupt controller when the INTINDEX bit in the QEIRIS register is set 1 0 RW INTINDE...

Page 1767: ...d Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x0000 000...

Page 1768: ...Description Value An interrupt has not occurred 0 The index pulse has occurred 1 This bit is cleared by writing a 1 to the INTINDEX bit in the QEIISC register 0 RO INTINDEX 0 June 18 2014 1768 Texas I...

Page 1769: ...reserved bit should be preserved across a read modify write operation 0x0000 000 RO reserved 31 4 Phase Error Interrupt Description Value No interrupt has occurred or the interrupt is masked 0 The INT...

Page 1770: ...e INTINDEX bits in the QEIRIS register and the QEIINTEN registers are set providing an interrupt to the interrupt controller 1 This bit is cleared by writing a 1 Clearing this bit also clears the INTI...

Page 1771: ...faults to an alternate function on reset In this case the GPIO port name is followed by the default alternate function To see a complete list of possible functions for each pin see Table 26 5 on page...

Page 1772: ...sible for a signal to be on multiple pins each possible pin assignment is listed The Pin Mux column indicates the GPIO and the encoding needed in the PMCx bit field in the GPIOPCTL register Table 26 4...

Page 1773: ...comparator 2 output TTL O C2o I2 C module 8 clock Note that this signal has an active pull up The corresponding port pin should not be configured as open drain OD I O I2C8SCL SSI module 2 frame signa...

Page 1774: ...ata Carrier Detect modem status input signal TTL I U1DCD GPIO port E bit 1 TTL I O PE1 14 Analog to digital converter input 2 Analog I AIN2 UART module 1 Data Set Ready modem output control line TTL I...

Page 1775: ...put Analog I C1 EPI module 0 signal 7 TTL I O EPI0S7 UART module 7 receive TTL I U7Rx Positive supply for I O and some logic Power VDD 26 GPIO port Q bit 3 TTL I O PQ3 27 EPI module 0 signal 23 TTL I...

Page 1776: ...Clk 16 32 Bit Timer 1 Capture Compare PWM 0 TTL I O T1CCP0 UART module 4 receive TTL I U4Rx GPIO port A bit 3 TTL I O PA3 36 I2 C module 8 data OD I O I2C8SDA SSI module 0 frame signal TTL I O SSI0Fss...

Page 1777: ...Optionally used in Host mode by an external power source to indicate an error state by that power source TTL I USB0PFLT GPIO port F bit 0 TTL I O PF0 42 Ethernet 0 LED 0 TTL O EN0LED0 Motion Control M...

Page 1778: ...d some logic Power VDD 52 Ethernet PHY negative receive differential input TTL I O EN0RXIN 53 Ethernet PHY positive receive differential input TTL I O EN0RXIP 54 Ground reference for logic and I O pin...

Page 1779: ...66 Hibernation module oscillator crystal output Leave unconnected when using a single ended clock source Analog O XOSC1 67 Power source for the Hibernation module It is normally connected to the posit...

Page 1780: ...al 16 TTL I O EPI0S16 I2 C module 2 data OD I O I2C2SDA Motion Control Module 0 PWM Fault 3 TTL I M0FAULT3 USB data 0 TTL I O USB0D0 GPIO port L bit 1 TTL I O PL1 82 EPI module 0 signal 17 TTL I O EPI...

Page 1781: ...to signal the end of a USB transmit packet or register write operation TTL O USB0STP GPIO port B bit 3 TTL I O PB3 92 EPI module 0 signal 28 TTL I O EPI0S28 I2 C module 0 data OD I O I2C0SDA 16 32 Bit...

Page 1782: ...output based on a selected clock source Note that this signal is not synchronized to the System Clock TTL O DIVSCLK UART module 1 receive TTL I U1Rx GPIO port P bit 2 TTL I O PP2 103 EPI module 0 sign...

Page 1783: ...I module 0 signal 34 TTL I O EPI0S34 I2 C module 2 data OD I O I2C2SDA UART module 1 Data Terminal Ready modem status input signal TTL O U1DTR UART module 3 Request to Send modem flow control output l...

Page 1784: ...SCL SSI module 1 frame signal TTL I O SSI1Fss UART module 0 Clear To Send modem flow control input signal TTL I U0CTS Positive supply for I O and some logic Power VDD 122 GPIO port E bit 4 TTL I O PE4...

Page 1785: ...Analog I PE3 12 AIN0 Analog to digital converter input 1 Analog I PE2 13 AIN1 Analog to digital converter input 2 Analog I PE1 14 AIN2 Analog to digital converter input 3 Analog I PE0 15 AIN3 Analog...

Page 1786: ...K4 5 42 63 EN0LED0 Ethernet 0 LED 1 TTL O PF4 5 PK6 5 46 61 EN0LED1 Ethernet 0 LED 2 TTL O PF1 5 PK5 5 43 62 EN0LED2 Ethernet 0 Pulse Per Second PPS Output TTL O PG0 5 PJ0 5 49 116 EN0PPS Ethernet PHY...

Page 1787: ...odule 0 signal 27 TTL I O PB2 15 91 EPI0S27 EPI module 0 signal 28 TTL I O PB3 15 92 EPI0S28 EPI module 0 signal 29 TTL I O PP2 15 PN2 15 103 109 EPI0S29 EPI module 0 signal 30 TTL I O PP3 15 PN3 15 1...

Page 1788: ...5 data OD I O PB1 2 PB5 2 96 120 I2C5SDA I2 C module 6 clock Note that this signal has an active pull up The corresponding port pin should not be configured as open drain OD I O PA6 2 40 I2C6SCL I2 C...

Page 1789: ...7 8 128 NMI Main oscillator crystal input or an external clock reference input Analog I fixed 88 OSC0 Main oscillator crystal output Leave unconnected when using a single ended clock source Analog O f...

Page 1790: ...PF4 GPIO port G bit 0 TTL I O 49 PG0 GPIO port G bit 1 TTL I O 50 PG1 GPIO port H bit 0 TTL I O 29 PH0 GPIO port H bit 1 TTL I O 30 PH1 GPIO port H bit 2 TTL I O 31 PH2 GPIO port H bit 3 TTL I O 32 P...

Page 1791: ...I O 106 PP5 GPIO port Q bit 0 TTL I O 5 PQ0 GPIO port Q bit 1 TTL I O 6 PQ1 GPIO port Q bit 2 TTL I O 11 PQ2 GPIO port Q bit 3 TTL I O 27 PQ3 GPIO port Q bit 4 TTL I O 102 PQ4 4 87 k resistor 1 precis...

Page 1792: ...I module 3 clock TTL I O PQ0 14 PF3 14 5 45 SSI3Clk SSI module 3 frame signal TTL I O PQ1 14 PF2 14 6 44 SSI3Fss SSI Module 3 Bi directional Data Pin 0 SSI3TX in Legacy SSI Mode TTL I O PQ2 14 PF1 14...

Page 1793: ...I O PM5 73 TMPR2 Tamper signal 3 TTL I O PM4 74 TMPR3 JTAG TMS and SWDIO TTL I PC1 1 99 TMS Trace clock TTL O PF3 15 45 TRCLK Trace data 0 TTL O PF2 15 44 TRD0 Trace data 1 TTL O PF1 15 43 TRD1 Trace...

Page 1794: ...TL O PN2 2 PD6 1 109 127 U2RTS UART module 2 receive TTL I PA6 1 PD4 1 40 125 U2Rx UART module 2 transmit TTL O PA7 1 PD5 1 41 126 U2Tx UART module 3 Clear To Send modem flow control input signal TTL...

Page 1795: ...n external element USB connector indicates the initial state of the USB controller pulled down is the A side of the cable and pulled up is the B side Analog I PB0 95 USB0ID Asserted by the external PH...

Page 1796: ...ecified in Table 27 15 on page 1834 Power fixed 87 115 VDDC A reference voltage used to specify the voltage at which the ADC converts to a maximum value This pin is used in conjunction with GNDA The v...

Page 1797: ...converter input 16 Analog I 18 AIN16 Analog to digital converter input 17 Analog I 19 AIN17 Analog to digital converter input 18 Analog I 20 AIN18 Analog to digital converter input 19 Analog I 21 AIN1...

Page 1798: ...TTL O 46 61 EN0LED1 Ethernet 0 LED 2 TTL O 43 62 EN0LED2 Ethernet 0 Pulse Per Second PPS Output TTL O 49 116 EN0PPS Ethernet PHY negative receive differential input TTL I O 53 EN0RXIN Ethernet PHY po...

Page 1799: ...module 0 signal 15 TTL I O 78 EPI0S15 EPI module 0 signal 16 TTL I O 81 EPI0S16 EPI module 0 signal 17 TTL I O 82 EPI0S17 EPI module 0 signal 18 TTL I O 83 EPI0S18 EPI module 0 signal 19 TTL I O 84 EP...

Page 1800: ...6 93 T1CCP1 16 32 Bit Timer 2 Capture Compare PWM 0 TTL I O 37 78 T2CCP0 16 32 Bit Timer 2 Capture Compare PWM 1 TTL I O 38 77 T2CCP1 16 32 Bit Timer 3 Capture Compare PWM 0 TTL I O 40 76 125 T3CCP0 1...

Page 1801: ...gnal 3 TTL I O 74 TMPR3 Power source for the Hibernation module It is normally connected to the positive terminal of a battery and serves as the battery backup Hibernation module power source supply P...

Page 1802: ...ll up The corresponding port pin should not be configured as open drain OD I O 61 I2C4SCL I2 C module 4 data OD I O 60 I2C4SDA I2 C module 5 clock Note that this signal has an active pull up The corre...

Page 1803: ...e 0 PWM Generator 0 TTL O 42 M0PWM0 Motion Control Module 0 PWM 1 This signal is controlled by Module 0 PWM Generator 0 TTL O 43 M0PWM1 Motion Control Module 0 PWM 2 This signal is controlled by Modul...

Page 1804: ...Analog Comparators etc These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions VDDA pins must be supplied with a voltage that meets the speci...

Page 1805: ...onal Data Pin 0 SSI2TX in Legacy SSI Mode TTL I O 2 SSI2XDAT0 SSI Module 2 Bi directional Data Pin 1 SSI2RX in Legacy SSI Mode TTL I O 1 SSI2XDAT1 SSI Module 2 Bi directional Data Pin 2 TTL I O 128 SS...

Page 1806: ...status input signal TTL I 13 109 U1DCD UART module 1 Data Set Ready modem output control line TTL I 14 110 U1DSR UART module 1 Data Terminal Ready modem status input signal TTL O 12 111 U1DTR UART mod...

Page 1807: ...fferential data pin D per USB specification for USB0 Analog I O 93 USB0DM Bidirectional differential data pin D per USB specification for USB0 Analog I O 94 USB0DP Optionally used in Host mode to cont...

Page 1808: ...BUS 96 PB1 EPI0S27 USB0STP T5CCP0 I2C0SCL 91 PB2 EPI0S28 USB0CLK T5CCP1 I2C0SDA 92 PB3 SSI1Fss I2C5SCL U0CTS AIN10 121 PB4 SSI1Clk I2C5SDA U0RTS AIN11 120 PB5 TCK SWCLK 100 PC0 TMS SWDIO 99 PC1 TDI 98...

Page 1809: ...EPI0S1 U4Tx AIN17 19 PK1 EPI0S2 U4RTS AIN18 20 PK2 EPI0S3 U4CTS AIN19 21 PK3 EPI0S32 M0PWM6 EN0LED0 I2C3SCL 63 PK4 EPI0S31 M0PWM7 EN0LED2 I2C3SDA 62 PK5 EPI0S25 M0FAULT1 EN0LED1 I2C4SCL 61 PK6 EPI0S2...

Page 1810: ...PP2 EPI0S30 USB0DIR RTCCLK U0DCD U1CTS 104 PP3 USB0D7 U0DSR U3RTS 105 PP4 USB0D6 I2C2SCL U3CTS 106 PP5 EPI0S20 SSI3Clk 5 PQ0 EPI0S21 SSI3Fss 6 PQ1 EPI0S22 SSI3XDAT0 11 PQ2 EPI0S23 SSI3XDAT1 27 PQ3 DI...

Page 1811: ...2 PD2 AIN13 PD1 AIN14 PD0 AIN15 PK0 AIN16 PK1 AIN17 PK2 AIN18 PK3 AIN19 PE1 AIN2 PE0 AIN3 PD7 AIN4 PD6 AIN5 PD5 AIN6 PD4 AIN7 PE5 AIN8 PE4 AIN9 PC6 C0 PC7 C0 PC5 C1 PC4 C1 PP0 C2 PP1 C2 PD2 C2o PA0 CA...

Page 1812: ...EPI0S26 PB2 EPI0S27 PB3 EPI0S28 PK5 EPI0S31 PK4 EPI0S32 PL5 EPI0S33 PN4 EPI0S34 PN5 EPI0S35 PC7 EPI0S4 PC6 EPI0S5 PC5 EPI0S6 PC4 EPI0S7 PA6 EPI0S8 PA7 EPI0S9 PB2 I2C0SCL PB3 I2C0SDA PG0 I2C1SCL PG1 I2...

Page 1813: ...k PA3 SSI0Fss PA4 SSI0XDAT0 PA5 SSI0XDAT1 PA6 SSI0XDAT2 PA7 SSI0XDAT3 PB5 SSI1Clk PB4 SSI1Fss PE4 SSI1XDAT0 PE5 SSI1XDAT1 PD4 SSI1XDAT2 PD5 SSI1XDAT3 PD3 SSI2Clk PD2 SSI2Fss PD1 SSI2XDAT0 PD0 SSI2XDAT...

Page 1814: ...3 PP2 U0DTR PA0 U0Rx PA1 U0Tx PB1 U1Tx PK3 U4CTS PK2 U4RTS PC6 U5Rx PC7 U5Tx PP0 U6Rx PP1 U6Tx PC4 U7Rx PC5 U7Tx PB3 USB0CLK PL0 USB0D0 PL1 USB0D1 PL2 USB0D2 PL3 USB0D3 PL4 USB0D4 PL5 USB0D5 PP5 USB0D...

Page 1815: ...4 I2C2SDA PB0 PB4 I2C5SCL PB1 PB5 I2C5SDA PA4 PD0 I2C7SCL PA5 PD1 I2C7SDA PA2 PD2 I2C8SCL PA3 PD3 I2C8SDA PF3 PQ0 SSI3Clk PF2 PQ1 SSI3Fss PF1 PQ2 SSI3XDAT0 PF0 PQ3 SSI3XDAT1 PF4 PP0 SSI3XDAT2 PA4 PM0...

Page 1816: ...cular system implementation for devices that are in a 128 pin TQFP package Two options are shown in the table an acceptable practice and a preferred practice for reduced power consumption and improved...

Page 1817: ...Ethernet Phy if no code is present in the flash and a 24 25Mhz crystal is attached to the OSC0 1 pins b PA1 UART0TX may be enabled as an output by the ROM boot loader if no code is present in the fla...

Page 1818: ...f any voltage higher than maximum rated voltages to this high impedance circuit Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level see Connection...

Page 1819: ...b C W 0 2 JT Thermal metric junction to top of package C W 22 1 JB Thermal metric junction to board C TC P JT c TPCB P JB d TA P JA e TB P JB fg TJ Junction temperature formula a For more details abou...

Page 1820: ...esigned with Slow GPIO Pads PJ1 All other GPIOs have a fast GPIO pad type Note Port pins PL6 and PL7 operate as Fast GPIO pads but have 4 mA drive capability only GPIO register controls for drive stre...

Page 1821: ...VIH nA 4 1 Slow GPIO high level input current a I IH V 0 35 VDD 0 Slow GPIO low level input voltage VIL nA 1 Slow GPIO low level input current a I IL V 0 49 Slow GPIO Input Hysteresis VHYS V 2 4 Slow...

Page 1822: ...nuous current sink of 18 mA is required then operation is limited to 0 to 75 C in order to meet the standard 10 year reliability At 105 C I O configured for continuous drive meet the standard 2 5 year...

Page 1823: ...ditions CL GND pin Table 27 11 Load Conditions Load Value CL Signals 30 pF EPI0S 35 0 SDRAM interface EPI0S 35 0 General Purpose interface EPI0S 35 0 Host Bus interface 40 pF EPI0S 35 0 PSRAM interfac...

Page 1824: ...fall to Data Valid from High Z 10 mA drive ns 14 11 TCK fall to Data Valid from High Z 12 mA drive ns 20 14 TCK fall to Data Valid from Data Valid 2 mA drive TTDO_DV J12 ns 26 10 TCK fall to Data Vali...

Page 1825: ...JTAG Test Access Port TAP Timing TDO Output Valid TCK TDO Output Valid J12 TDO TDI TMS TDI Input Valid TDI Input Valid J13 J9 J10 TMS Input Valid J9 J10 TMS Input Valid J11 J7 J8 J8 J7 1825 June 18 20...

Page 1826: ...27 6 1 VDDA Levels The VDDA supply has three monitors Power On Reset POR Power OK POK Brown Out Reset BOR The POR monitor is used to keep the analog circuitry in reset until the VDDA supply has reach...

Page 1827: ...se registers Figure 27 4 on page 1827 shows the relationship between VDDA POK POR and a BOR event Figure 27 4 Power and Brown Out Assertions vs VDDA Levels P1 VDDA P5RISE P4 POR POK BOR P4 1 VDDAMIN 1...

Page 1828: ...its control both BOR events BORIM bit in the Interrupt Mask Control IMC register System Control offset 0x054 VDDA_UBOR0 and VDD_UBOR0 bits in the Power Temperature Cause PWRTC register Please refer to...

Page 1829: ...shows the response of the BOR and the POR circuit to glitches on the VDD supply Figure 27 7 POR BOR VDD Glitch Response 27 6 4 2 VDD Droop Response Figure 27 8 on page 1830 shows the response of the B...

Page 1830: ...Figure 27 8 POR BOR VDD Droop Response June 18 2014 1830 Texas Instruments Production Data Electrical Characteristics...

Page 1831: ...ation b These values are based on simulation c Timing values are dependent on the VDD power down ramp rate d This is the delay from the time POR is released until the reset vector is fetched e This pa...

Page 1832: ...ernal Reset Timing RST RST Package Pin Reset Internal R4 R5 R2 Figure 27 12 Software Reset Timing Software Reset Reset Internal R6 Figure 27 13 Watchdog Reset Timing Watchdog Reset Reset Internal R7 J...

Page 1833: ...Figure 27 14 MOSC Failure Reset Timing MOSC Fail Reset Reset Internal R8 1833 June 18 2014 Texas Instruments Production Data Tiva TM4C1294NCPDT Microcontroller...

Page 1834: ...ternal power supply a CLDO m 100 0 Filter capacitor equivalent series resistance ESR nH 0 5 Filter capacitor equivalent series inductance ESL V 1 27 1 2 1 13 LDO output voltage Run mode VLDO mA 250 50...

Page 1835: ...the PLLFREQ1 register must be set to 0x3 rather than using the PSYSDIV field in the RSCLKCFG register for the divisor 27 9 1 1 PLL Configuration The PLL is disabled by default during power on reset a...

Page 1836: ...LLFREQn registers see page 292 The internal translation provides a translation within 1 of the targeted PLL VCO frequency Table 5 7 on page 238 shows the actual PLL frequency and error for a given cry...

Page 1837: ...ific temperature s 1 PIOSC startup time a TSTART a PIOSC startup time is part of reset and is included in the internal reset timeout value TIRTOUT given in Table 27 14 on page 1831 Note that the TSTAR...

Page 1838: ...ed from the time the oscillator is enabled to when it reaches a stable point of oscillation such that the internal clock is valid e Only valid for recommended supply conditions Measured with OSCDRV bi...

Page 1839: ...SR 2 An estimation of the typical power delivered to the crystal is based on the CL FP and ESR parameters of the crystal in the circuit as calculated by the OSCPWR equation Ensure that the value calcu...

Page 1840: ...rystal Parameters Crystal Spec Tolerance Stability Freq MHz PKG Size mm x mm Holder MFG Part MFG Max Values Typical Values Rs k C 2 pF C 1 pF C L pf Max Dl W ESR L1 mH C1 fF C0 pF 132 0 12 12 8 500 30...

Page 1841: ...n 159 1 5 a 12 12 10 1000 40 3 2 12 8 3 00 15 30 ppm 25 13 3 x 4 85 HC 49 UP ECX 6593 25 000M Ecliptek 181 2 12 12 8 200 50 8 70 4 70 1 10 20 30 ppm 25 3 2 x 2 5 NX3225GA NX3225GA 25 000MHZ STD CRG 2...

Page 1842: ...ing when PLL is bypassed Fsysadc 27 9 7 System Clock Specification with USB Operation Table 27 26 System Clock Characteristics with USB Operation Unit Max Nom Min Parameter Name Parameter MHz 30 Syste...

Page 1843: ...D3 s 39 Time to restore LDO to 1 2 V in Sleep mode TLDO D4 s 5 Time to restore Flash to active state from low power state in Sleep mode TFLASH D5 s 15 Time to restore SRAM to active state from low po...

Page 1844: ...Min Parameter Name Parameter Parameter No s 15 Time to restore SRAM to active state from standby state TSRAMSTBYDS D14 a Deep Sleep Clock can vary See page 281 for the Deep Sleep Clock options June 18...

Page 1845: ...ation Module Characteristics Unit Max Nom Min Parameter Name Parameter Parameter No ns 100 WAKE assertion time TWAKE H1 Hibernation clock period 1 WAKE assert to HIB desassert wake up time TWAKE_TO_HI...

Page 1846: ...Figure 27 15 Hibernation Module Timing HIB WAKE VDD POR H2 H3 H4 H1 June 18 2014 1846 Texas Instruments Production Data Electrical Characteristics...

Page 1847: ...64 bits data b TPROG64 ms 15 8 Page erase time 1k cycles TERASE ms 40 15 Page erase time 10k cycles ms 500 75 Page erase time 100k cycles ms 25 10 Mass erase time 1k cycles TME ms 70 20 Mass erase tim...

Page 1848: ...f data a copy to the copy buffer is required the copy buffer requires an erase and greater than 90 of EEPROM endurance used system clocks 9 4 EWS 7 2 EWS Read access time d ETREAD ms 15 8 Mass erase t...

Page 1849: ...controls except for the GPIODR12R register apply to these port pins Table 27 34 Fast GPIO Module Characteristics abcd Unit Max Nom Min Parameter Name Parameter pF 50 Capacitive loading for measuremen...

Page 1850: ...ll down resistor is disabled h Time measured from 20 to 80 of VDD i Time measured from 80 to 20 of VDD Table 27 35 Slow GPIO Module Characteristics abc Unit Max Nom Min Parameter Name Parameter pF 50...

Page 1851: ...x negative injection if not voltage protected d IINJ a VIN must be within the range specified in Table 27 1 on page 1818 Leakage current outside of this maximum voltage is not guaranteed and can resul...

Page 1852: ...able 27 44 on page 1861 c I O pads should be protected if at any point the IO voltage has a possibility of going outside the limits shown in the table If the part is unpowered the IO pad Voltage or Cu...

Page 1853: ...ition Parameter Name Parameter ns 3 2 12 mA drive CL 30 pF EPI Rise Time from 20 to 80 of VDD TSDRAMR ns 3 2 12 mA drive CL 30 pF EPI Fall Time from 80 to 20 of VDD TSDRAMF Table 27 40 EPI SDRAM Inter...

Page 1854: ...ster may be loaded prior to the auto refresh cycles if desired 3 JEDEC and PC100 specify three clocks 4 Outputs are guaranteed High Z after command is issued E9 E10 E11 E12 E1 E2 E3 NOP AREF NOP Activ...

Page 1855: ...meter No ns 10 Read data set up time TISU E14 ns 0 Read data hold time TIH E15 ns 3 6 WRn to write data valid TDV E16 EPI Clocks 1 Data hold from WRn invalid TDI E17 ns 4 ALE CSn to output valid TOV E...

Page 1856: ...in Host Bus 16 mode only E21 E18 E22 E19 E20 E14 E15 E23 Figure 27 22 Host Bus 8 16 Asynchronous Mode Write Timing Data ALE EPI0S30 CSn EPI0S30 WRn EPI0S29 RDn Oen EPI0S28 Address Data E18 E18 E16 E2...

Page 1857: ...available in Host Bus 16 mode only Table 27 42 EPI General Purpose Interface Characteristics Unit Max Nom Min Parameter Name Parameter Parameter No ns 16 67 General Purpose Clock period TCK E25 ns 8...

Page 1858: ...Name Parameter Parameter No ns 20 EPI_CLK period TEPICLK E33 ns 1 8 EPI_CLK rise or fall time TRTFT E34 ns 20 4 5 Falling EPI_CLK to Address Write Data or Control output valid a TOV E35 ns 2 Falling...

Page 1859: ...Burst Read EPICLK EPI0S31 EPI0S 19 0 ALE CSn EPI0S 15 0 ADDRESS E34 E33 E36 E39 WRn EPI0S29 BSELn iRDY EPI0S32 DATA E35 E40 E37 E38 E36 E36 1859 June 18 2014 Texas Instruments Production Data Tiva TM4...

Page 1860: ...t Write EPICLK EPI0S31 EPI0S 19 0 ALE CSn EPI0S 15 0 WRn EPI0S29 BSELn iRDY EPI0S32 ADDRESS DATA DATA DATA DATA E36 E33 E34 E35 E35 E35 E36 E36 E39 E40 June 18 2014 1860 Texas Instruments Production D...

Page 1861: ...input voltage internal reference df V VREFA GNDA Single ended full scale analog input voltage external reference e V VREFA GNDA VREFA GNDA Differential full scale analog input voltage external referen...

Page 1862: ...sensor slope at 40 C to 85 C ambient industrial temperature part 40 C to 105 C ambient extended temperature part STSENS C 5 Temperature sensor accuracy at y 40 C to 85 C ambient industrial temperatur...

Page 1863: ...ed internally r ADC dynamic characteristics are measured using low noise board design with low noise reference voltage 74dB noise level in signal BW and low noise analog supply voltage Board noise and...

Page 1864: ...om trigger to start of conversion TLT SYSTEM PERFORMANCE when using external reference mn bits 12 Resolution N LSB 3 0 1 5 Integral nonlinearity error over full input range INL LSB 2 0 1 0 o 0 8 Diffe...

Page 1865: ...ecification l ADC conversion time Tc includes the ADC sample time Ts m Low noise environment is assumed in order to obtain values close to spec Board must have good ground isolation between analog and...

Page 1866: ...DC Input Equivalency Rs Cs CADC Pin VS IL Zs Clamp RADC Input PAD Equivalent Circuit ZADC Input PAD Equivalent Circuit RADC Input PAD Equivalent Circuit RADC 12 bit SAR ADC Converter Pin Pin Tiva Micr...

Page 1867: ...Valid Time from edge of SSIClk TTXDSOV S10 ns 37 4 e Slave Mode Slave Tx Data Output to Master Hold Time from next SSIClk TTXDSOH S11 ns 0 Slave Mode Rx Data In from master setup time TRXDSSU S13 ns 3...

Page 1868: ...SSIRx MSB LSB S2 S3 S1 S5 4 to 16 bits S4 Figure 27 31 Master Mode SSI Timing for SPI Frame Format FRF 00 with SPH 1 SSIClk SPO 0 SSITx to slave SSIRx from slave SSIClk SPO 1 S2 S1 S5 SSIFss LSB S3 S...

Page 1869: ...time c TCLKF S19 ns 4 04 Master Mode Master SSInXDATn Data Output to slave Valid Time from edge of SSIClk TTXDMOV S20 ns 0 60 Master Mode Master SSInXDATn Data Output to slave Hold Time after next SS...

Page 1870: ...6 1 TPR 1 Data Valid master a Values depend on the value programmed into the TPR bit in the I2 C Master Timer Period I2CMTPR register a TPR programmed for the maximum I2CSCL frequency TPR 0x2 results...

Page 1871: ...VTPTD_10 mV 200 10Base T Receive threshold VTH1 27 19 2 Clock Characteristics Table 27 50 MOSC 25 MHz Crystal Specification a Unit Max Nom Min Parameter Name Parameter Parameter No MHz 25 Frequency FM...

Page 1872: ...the PMD output pin ab TEN N16 ns 110 Time from software reset of the PHY to energy on the PMD output pin TSWRST N17 a The PHY is enabled through System Control by setting the P0 bit in the PCEPHY regi...

Page 1873: ...Ethernet transformer magnetics can affect this parameter Figure 27 37 100 Base TX Transmit Timing N39 N39 PMD Output Pair Eye Pattern N38 PMD Output Pair 90 10 90 10 90 10 90 10 N38 N38 N38 1 rise 1 f...

Page 1874: ...TBRSTW N76 Figure 27 39 Auto Negotiation Fast Link Pulse Timing Fast Link Pulse s N75 FLP Burst Clock Pulse Data Pulse Clock Pulse N74 N74 N73 N72 FLP Burst N76 N76 Table 27 56 100Base TX Signal Dete...

Page 1875: ...eter Name Parameter Parameter No Timings with respect to external clock source input to USB0CLK ns 4 8 Setup time control in USB0DIR USB0NXT TSUC U1 ns 3 5 Setup Time data in USB0Dn TSUD U2 ns 0 Hold...

Page 1876: ...Figure 27 41 ULPI Interface Timing Diagram USB0CLK USB0STP USB0Dn Write USB0DIR USB0NXT USB0Dn Read U1 U2 U3 U4 U5 U6 June 18 2014 1876 Texas Instruments Production Data Electrical Characteristics...

Page 1877: ...ternal voltage reference is used it should be set to a mid supply level When operating in Sleep Deep Sleep modes the Analog Comparator module should be disabled or the external voltage inputs set to d...

Page 1878: ...nit VIREF Max Ideal VIREF VIREF Min VREF Value V 0 074 0 000 0 000 0x0 V 0 223 0 149 0 076 0x1 V 0 372 0 298 0 225 0x2 V 0 521 0 448 0 374 0x3 V 0 670 0 597 0 523 0x4 V 0 820 0 746 0 672 0x5 V 0 969 0...

Page 1879: ...5 MnFAULTn De Assertion to PWM Active b TFLTMIN a This parameter value can vary depending on the PWM clock frequency which is controlled by the System Clock and a programmable divider field in the PW...

Page 1880: ...0 5 29 3 12 7 11 5 10 1 5 10 PIOSC 1 MHz mA 106 0 96 6 78 6 77 6 76 0 68 1 MOSC with PLL 120 MHz VDD 3 3 V VDDA 3 3 V mA 79 2 67 9 50 8 49 8 48 2 40 0 MOSC with PLL 60 MHz Peripherals All ON except MA...

Page 1881: ...with PLL 60 MHz Peripherals All ON including MAC but not PHY mA 45 1 34 5 18 5 17 5 16 2 10 6 PIOSC d 16 MHz LDO 1 2 V mA 38 7 28 0 12 0 10 9 9 60 4 47 PIOSC d 1 MHz mA 95 4 84 9 68 1 67 1 65 6 54 4...

Page 1882: ...A 25 3 17 1 4 60 3 83 2 83 2 60 LFIOSC 30 kHz Peripherals All ON LDO 1 2 V mA 22 7 15 9 5 53 4 88 4 05 4 53 PIOSC 16 MHz VDD 3 3 V VDDA 3 3 V mA 20 7 13 3 2 46 1 69 0 762 0 614 LFIOSC 30 kHz Periphera...

Page 1883: ...f A 2 14 1 62 1 69 1 44 1 20 1 04 VBAT 3 0 V VDD 0 V VDDA 0 V System Clock OFF Hibernate Module 32 768 kHz Hibernate mode external wake RTC disabled IHIB_NORTC A 2 33 1 75 1 82 1 54 1 29 1 12 VBAT 3 0...

Page 1884: ...ible Deep Sleep current is not achieved f See the section called LDO Power Control on page 244 for information on lowering the LDO voltage to 0 9 V Table 27 64 Peripheral Current Consumption Units Nom...

Page 1885: ...volutionary stages of product development from engineering prototypes XM4C through fully qualified production devices TM4C Device development evolutionary flow XM4C Experimental device that is not nec...

Page 1886: ...mber is the last number in the part number in this example 3 The DID0 register identifies the version of the microcontroller as shown in the table below Combined the MAJOR and MINOR bit fields indicat...

Page 1887: ...D FLATPACK 64 33 0 13 NOM Gage Plane 0 25 0 45 0 75 Seating Plane 0 05 MIN 4087726 A 11 95 0 23 0 13 65 32 96 1 12 40 TYP 128 97 SQ SQ 0 95 1 05 15 90 16 10 13 95 1 20 MAX 14 05 0 08 0 40 M 0 05 0 5 N...

Page 1888: ...conversion plan has not been defined Pb Free RoHS TI s terms Lead Free or Pb Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances including the...

Page 1889: ...better integrate information from third parties TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or...

Page 1890: ...sponsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related inf...

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