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Register 11: Flash Peripheral Properties (FLASHPP), offset 0xFC0
Flash Peripheral Properties (FLASHPP)
Base 0x400F.D000
Offset 0xFC0
Type RO, reset 0xF014.01FF
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
MAINSS
EESS
reserved
DFA
FMM
PFC
reserved
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
1
0
1
0
0
0
0
0
0
0
1
1
1
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SIZE
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
RO
reserved
31
Prefetch Buffer Mode
Description
Value
Single set of 2x256-bit buffers used.
0
Two sets of 2x256-bit prefetch buffers are available to use and
may be enabled through the
FLASHCONF
register.
1
0x1
RO
PFC
30
Flash Mirror Mode
Description
Value
Mirror Mode not available.
0
Flash Mirror Mode is available to be enabled or disabled by user
through
FLASHCONF
register.
1
0x1
RO
FMM
29
DMA Flash Access
Note:
µDMA can only access flash in Run Mode (not available in
low power modes).
Description
Value
DMA cannot be used to access Flash
0
DMA may access the Flash memory range specified by the
FLASHDMAST
and
FLASHDMASZ
registers
1
0x1
RO
DFA
28
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
RO
reserved
27:23
June 18, 2014
642
Texas Instruments-Production Data
Internal Memory