Texas Instruments TM4C1294NCPDT, Datasheet

Page: 591 / 1890

Register 23: HIB Tamper I/O Control (HIBTPIO), offset 0x410
The HIB Tamper I/O Control (HIBTPIO) register provides control of the Tamper I/O.
Note: Except for the HIBIO and a portion of the HIBIC register, all other Hibernation module
registers are on the Hibernation module clock domain and have special timing requirements.
Software should make use of the
WRC
bit in the HIBCTL register to ensure that the required
timing gap has elapsed. If the
WRC
bit is clear, any attempted write access is ignored. See
“Register Access Timing” on page 535. The HIBIO register and bits
RSTWK
,
PADIOWK
and
WC
of the HIBIC register do not require waiting for write to complete. Because these registers
are clocked by the system clock, writes to these registers/bits are immediate.
Writing to registers other than the HIBCTL and HIBIM before the
CLK32EN
bit in the HIBCTL
register has been set may produce unexpected results.
Note: Errant writes to the Tamper registers are protected by the Hibernate HIBLOCK register.
HIB Tamper I/O Control (HIBTPIO)
Base 0x400F.C000
Offset 0x410
Type RW, reset 0x0000.0000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
EN2 LEV2 PUEN2 GFLTR2 reserved EN3 LEV3 PUEN3 GFLTR3 reserved
RW RW RW RW RO RO RO RO RW RW RW RW RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
EN0 LEV0 PUEN0 GFLTR0 reserved EN1 LEV1 PUEN1 GFLTR1 reserved
RW RW RW RW RO RO RO RO RW RW RW RW RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Description Reset Type Name Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation. 0 RO reserved 31:28
TMPR3 Glitch Filtering
Description Value
A trigger match level is ignored until the
TMPR3
signal is stable
for two hibernate clocks.
0
A trigger match level is ignored until the
TMPR3
signal is stable
for 3,071 Hibernate Clocks (93.7ms using 32.768 kHz).
1
0 RW GFLTR3 27
TMPR3 Internal Weak Pull-up Enable
Description Value
Pull-up disabled 0
Pull-up enabled 1
0 RW PUEN3 26
591 June 18, 2014
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TM4C1294NCPDT Microcontroller