Texas Instruments TM4C1294NCPDT, Datasheet

Page: 528 / 1890

Register 3: System Exception Masked Interrupt Status (SYSEXCMIS), offset
0x008
The SYSEXCMIS register is the masked interrupt status register. On a read, this register gives the
current masked status value of the corresponding interrupt. A write has no effect.
System Exception Masked Interrupt Status (SYSEXCMIS)
Base 0x400F.9000
Offset 0x008
Type RO, reset 0x0000.0000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FPIDCMIS FPDZCMIS FPIOCMIS FPUFCMIS FPOFCMIS FPIXCMIS
reserved
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Description Reset Type Name Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation. 0x0000.00 RO reserved 31:6
Floating-Point Inexact Exception Masked Interrupt Status
Description Value
An interrupt has not occurred or is masked. 0
An unmasked interrupt was signaled due to an inexact
exception. 1
This bit is cleared by writing a 1 to the
FPIXCIC
bit in the SYSEXCIC
register.
0 RO FPIXCMIS 5
Floating-Point Overflow Exception Masked Interrupt Status
Description Value
An interrupt has not occurred or is masked. 0
An unmasked interrupt was signaled due to an overflow
exception. 1
This bit is cleared by writing a 1 to the
FPOFCIC
bit in the SYSEXCIC
register.
0 RO FPOFCMIS 4
Floating-Point Underflow Exception Masked Interrupt Status
Description Value
An interrupt has not occurred or is masked. 0
An unmasked interrupt was signaled due to an underflow
exception. 1
This bit is cleared by writing a 1 to the
FPUFCIC
bit in the SYSEXCIC
register.
0 RO FPUFCMIS 3
June 18, 2014 528
Texas Instruments-Production Data
Processor Support and Exception Module