Texas Instruments TM4C1294NCPDT, Datasheet

Page: 167 / 1890

Register 56: Interrupt Control and State (INTCTRL), offset 0xD04
Note: This register can only be accessed from privileged mode.
The INCTRL register provides a set-pending bit for the NMI exception, and set-pending and
clear-pending bits for the PendSV and SysTick exceptions. In addition, bits in this register indicate
the exception number of the exception being processed, whether there are preempted active
exceptions, the exception number of the highest priority pending exception, and whether any interrupts
are pending.
When writing to INCTRL , the effect is unpredictable when writing a 1 to both the
PENDSV
and
UNPENDSV
bits, or writing a 1 to both the
PENDSTSET
and
PENDSTCLR
bits.
Interrupt Control and State (INTCTRL)
Base 0xE000.E000
Offset 0xD04
Type RW, reset 0x0000.0000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
VECPEND reserved ISRPEND ISRPRE reserved
PENDSTCLR PENDSTSET UNPENDSV
PENDSV reserved NMISET
RO RO RO RO RO RO RO RO RO WO RW WO RW RO RO RW Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
VECACT reserved RETBASE VECPEND
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Description Reset Type Name Bit/Field
NMI Set Pending
Description Value
On a read, indicates an NMI exception is not pending.
On a write, no effect.
0
On a read, indicates an NMI exception is pending.
On a write, changes the NMI exception state to pending.
1
Because NMI is the highest-priority exception, normally the processor
enters the NMI exception handler as soon as it registers the setting of
this bit, and clears this bit on entering the interrupt handler. A read of
this bit by the NMI exception handler returns 1 only if the
NMI
signal is
reasserted while the processor is executing that handler.
0 RW NMISET 31
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation. 0x0 RO reserved 30:29
PendSV Set Pending
Description Value
On a read, indicates a PendSV exception is not pending.
On a write, no effect.
0
On a read, indicates a PendSV exception is pending.
On a write, changes the PendSV exception state to pending.
1
Setting this bit is the only way to set the PendSV exception state to
pending. This bit is cleared by writing a 1 to the
UNPENDSV
bit.
0 RW PENDSV 28
167 June 18, 2014
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TM4C1294NCPDT Microcontroller