Texas Instruments TM4C1294NCPDT, Datasheet

Page: 1336 / 1890

Register 17: I
2
C Slave Interrupt Mask (I2CSIMR), offset 0x80C
This register controls whether a raw interrupt is promoted to a controller interrupt.
I2C Slave Interrupt Mask (I2CSIMR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
I2C 6 base: 0x400C.2000
I2C 7 base: 0x400C.3000
I2C 8 base: 0x400B.8000
I2C 9 base: 0x400B.9000
Offset 0x80C
Type RW, reset 0x0000.0000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
reserved
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DATAIM STARTIM STOPIM DMARXIM DMATXIM TXIM RXIM TXFEIM RXFFIM reserved
RW RW RW RW RW RW RW RW RW RO RO RO RO RO RO RO Type
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Description Reset Type Name Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation. 0 RO reserved 31:9
Receive FIFO Full Interrupt Mask
Description Value
The
RXFFRIS
interrupt is suppressed and not sent to the
interrupt controller.
0
The Receive FIFO Full interrupt is sent to the interrupt controller
when the
RXFFRIS
bit in the I2CSRIS register is set.
1
0 RW RXFFIM 8
Transmit FIFO Empty Interrupt Mask
Description Value
The
TXFERIS
interrupt is suppressed and not sent to the
interrupt controller.
0
The Transmit FIFO Empty interrupt is sent to the interrupt
controller when the
TXFERIS
bit in the I2CSRIS register is set.
1
0 RW TXFEIM 7
Receive FIFO Request Interrupt Mask
Description Value
The
RXRIS
interrupt is suppressed and not sent to the interrupt
controller.
0
The RX FIFO Request interrupt is sent to the interrupt controller
when the
RXRIS
bit in the I2CSRIS register is set.
1
0 RW RXIM 6
June 18, 2014 1336
Texas Instruments-Production Data
Inter-Integrated Circuit (I
2
C) Interface