Texas Instruments TLV320AIC3268EVM-U, User Manual

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AV_ENABLE
DV_ENABLE
AV_ENABLE
DV_ENABLE
DV_ENABLE
AV_ENABLE
BCLK1_DUT
WCLK1_DUT
DIN1_DUT
DOUT1_DUT
BCLK1
WCLK1
DIN1
DOUT1
MCLK_DUT
MCLK
BCLK2
WCLK2
DIN2
DOUT2
DOUT2_DUT
DIN2_DUT
WCLK2_DUT
BCLK2_DUT
TEST1
BCLK3
WCLK3
DIN3
DOUT3
GPIO1
GPIO2
GPIO3
GPIO3
GPIO4
GPIO4
TAS_WCLK
TAS_BCLK
6Wire1_EN
GPIO5
TEST2
+5V
GND GND GND
+5V
GND GND GND
+5V
GND GND GND
+5V
GND GND GND
+5V
GND
GND GND
GND
+5V
GND GND
GND
GND
0.1uF/16V
C54
10uF/6.3V
C55
10k
R47
0.1uF/16V
C56
10uF/6.3V
C57
10k
R48
0.1uF/16V
C58
10uF/6.3V
C59
10k
R49
0.1uF/16V
C60
10uF/6.3V
C61
10k
R50
0.1uF/16V
C62
10uF/6.3V
C63
10k
R51
0.1uF/16V
C64
10uF/6.3V
C65
10k
R52
47ufd/6.3V
C66
47uF/6.3V
C67
47uF/6.3V
C68
47uF/6.3V
C69
47ufd/6.3V
C70
47uF/6.3V
C71
TP69
TP1
TP2
JP22
1
2
3
JP23
3
2
1
TP62 TP63 TP64 TP65 TP66 TP67 TP68
TP3
TP4
TP5
GND
GND
GND
GND
TP6
TP7 TP8 TP9 TP10
GND
JP4
1 2
3
JP8
3 2 1
JP7
1 2 3
JP6
1 2 3
JP5
1 2 3
JP12
3
2 1
JP11
1 2
3
JP10
1 2
3
JP9
3
2 1
TP11 TP12 TP13 TP14
GND
GND
GND
GND
DNP
J2
1
2
3 4
5 6
GND
TP15 TP16
GND
0
R53
0
R54
GND
GND
GND
GND
JP13
1 2
3
JP14
3
2 1
JP15
3
2 1
JP16
1 2
3
gpio1/bclk3
TP17
gpio2/wclk3
TP18
gpio3/din3
TP19
gpio4/dout3
TP20
JP20
1 2 3
JP21
3 2
1
GND GND
GND
GND
GND
0.1uF/16V
C72
0.1uF/16V
C73
10k
R55
GND
DATA
CLOCK
SELECT
VDD
MIC3
1
2
3
4
5
6
GND
GND GND
GND GND
GND
GND
0.1uF/16V
C91
0.1uF/16V
C90
SELECT
CLOCK
DATA
VDD
MIC2
6
5
4
3
2
1
JP19
3 2 1
JP18
1 2 3
JP17
3 2 1
GND GND GND
GND
GND GND
GND GND
GND
GND
0.1uF/16V
C74
0.1uF/16V
C75
DATA
CLOCK
SELECT
VDD
MIC5
6
5
4
3
2
1
DATA
CLOCK
VDD
SELECT
MIC4
1
2
3
4
5
6
L;DN
11
C
C
JOHN FEDAK IV
JANUARY 31, 2014
AIP013C_Schematic.sbk
DESIGN LEAD
PAGE INFO:
FILENAME
DATE OF
DRAWN BY
SHEET
PCB REV
SCH REV
+1.8VA
+1.8VD
+3.3VA
+1.8V_CP
+3.3VIO
+3.3VIO
+3.3VIO +1.8VIO
+1.8VIO
+3.3VIO
IOVD2
IOVD1
IOVD2
GND
GND
GND
GND
GND
IOVD1
IOVD1
+1.8VIO
1.8V/400mA
VR3
1
2
3 4
5
TPS73618DBV
3.3V/400mA
VR5
1
2
3 4
5
TPS73633DBV
1.8V/400mA
VR1
5
4 3
2
1
TPS73618DBV
1.8V/400mA
VR2
1
2
3 4
5
TPS73618DBV
1.8V/400mA
VR4
1
2
3 4
5
TPS73618DBV
3.3V/400mA
VR6
5
4 3
2
1
TPS73633DBV
DNP
J3
SLIMbus
SATA
7
6
5
4
3
2
1
GND
B+
B-
GND
A+
GND
A-
Case
U23
8 7 6 5
4 3 2 1
TXB0102DCU
B
2
A
2
V
C
C
A
G
N
D
B
1
V
C
C
B
O
E
A
1
TLV320AIC3268RGC EVALUATION BOARD
LDOs & AIC3268 ANALOG OUTPUTS 5
LDO SUPPLIES
IOVD1: GPIO1: Dig_Mic 1,2 Data and BCLK3
GPIO2: ADC_MOD_CLK and WCLK3
GPIO5: Dig_Mic 3,4 Data
IOVD2: GPIO3: DIN3
GPIO4: DOUT3
Use same IOVD for IOVD1 and IOVD2.
BCLK3 -> GPIO2 (IOVD1)
WCLK3 -> GPIO1 (IOVD1)
DIN3 -> GPIO3 (IOVD2)
DOUT3 -> GPIO4 (IOVD2)
TI
TLV320AIC3268EVM-U EVM Schematics
www.ti.com
Figure 9. LDO Supplies and Analog Outputs
12 TLV320AIC3268EVM-U Evaluation Module SLAU564A – February 2014 – Revised February 2014
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