background image

3.3V

GND

GND

GND

33

R19

33

R11

33

R12

33

R13

33

R14

33

R15

33

R16

33

R52

GND

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

J22

IOR

RESET_5V

33

R8

33

R9

33

R10

A0
A1
A2

33

R51

33

R23

33

R21

CS

33

R18

VCCA

1

DIR

2

A1

3

A2

4

A3

5

A4

6

A5

7

A6

8

A7

9

A8

10

GND

11

GND

12

GND

13

B8

14

B7

15

B6

16

B5

17

B4

18

B3

19

B2

20

B1

21

OE

22

VCCB

23

VCCB

24

SN74LVC8T245DWR

U8

GND

1uF

C18

GND

1uF

C16

GND

10.0k

R97

3.3V

3.3V

GND

10.0k

R77

GND

3.3V

A0_5V
A1_5V
A2_5V

RESET_5V

A0_5V
A1_5V
A2_5V

VCC

TP2

Vuart

VCC

GND

GND

3.3V

GND

4.7k

R61

A1

1

VCCA

2

A2

3

A3

4

A4

5

A5

6

A6

7

A7

8

A8

9

OE

10

GND

11

B8

12

B7

13

B6

14

B5

15

B4

16

B3

17

B2

18

VCCB

19

B1

20

TXS0108EPWR

U4

33

R31

33

R32

33

R33

33

R34

33

R35

33

R36

33

R37

33

R38

GND

3.3V

D0_5V
D1_5V
D2_5V
D3_5V
D4_5V
D5_5V
D6_5V
D7_5V

D0
D1

D3
D4
D5
D6
D7

D2

GND

TP5

5010

XTAL2

XTAL2

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

J23

VCCA

1

DIR

2

A1

3

A2

4

A3

5

A4

6

A5

7

A6

8

A7

9

A8

10

GND

11

GND

12

GND

13

B8

14

B7

15

B6

16

B5

17

B4

18

B3

19

B2

20

B1

21

OE

22

VCCB

23

VCCB

24

SN74LVC8T245DWR

U9

GND

1uF

C19

GND

1uF

C17

GND

10.0k

R98

3.3V

3.3V

GND

10.0k

R79

GND

3.3V

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

J18

33

R48

33

R44

33

R46

33

R47

CD

RI

RI

RI_5V

RI_5V

A0
A1
A2

RI

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

J20

VCCA

1

DIR

2

A1

3

A2

4

A3

5

A4

6

A5

7

A6

8

A7

9

A8

10

GND

11

GND

12

GND

13

B8

14

B7

15

B6

16

B5

17

B4

18

B3

19

B2

20

B1

21

OE

22

VCCB

23

VCCB

24

SN74LVC8T245DWR

U7

GND

1uF

C15

GND

1uF

C13

GND

10.0k

R92

3.3V

3.3V

GND

GND

3.3V

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

J13

VCC

10.0k

R71

DTR

10.0k

R66

10.0k

R70

GND

OP

RTS

33

R45

33

R49

33

R50

33

R22

33

R20

DTR
RTS
OP

33

R43

D4

RESET diode

120

R62

3.3V

GND

VCC

1

2

3

4

S1

MR

4.7k

R68

3.3V

TP3
5010

GND

110

R24

D2

1

2
3
4
5

J5

GND

TX

RX

1uF

C8

GND

VCC

1uF

C6

GND

33

R55

GND

TP7

5V TXRDY

GND

TP8

TX

A

3

VCCA

1

B

4

DIR

5

GND

2

VCCB

6

SN74LVC1T45DBVT

U6

1uF

C14

GND

VCC

1uF

C12

GND

3.3V

33

R74

GND

TP10

5V RXRDY

GND

TP6

RXRDY

3.3V

4.7k

R67

0

R69

DNP

3.3V

33

R82

33

R83

33

R84

33

R86

33

R87

33

R88

33

R89

DTR 5V
RTS 5V
OP 5V

DTR 5V
RTS 5V
OP 5V

10.0k

R102

3.3V

10.0k

R103

3.3V

10.0k

R104

3.3V

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15
17
19

21

23
25
27
29

31

16
18
20
22
24
26
28
30
32

J12

D0

D1

D2

D3

D4

D5

D6

D7

GND

GND

A0

A1

A2

A0

A1

A2

GND

GND

GND

XU1

DNP

1uF

C1

0.1µF

C3

50V
0.01µF

C5

0

R56

0

R53

0

R59

DNP

MR-RESET

MR-RESET

30

R41

CD
DSR
CTS

CD
DSR
CTS

CD_5V
DSR_5V
CTS_5V

CD_5V
DSR_5V
CTS_5V

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

J2

D0_5V
D1_5V
D2_5V
D3_5V
D4_5V
D5_5V
D6_5V
D7_5V

3.3V

10.0k

R3

1

2

3

J1

GND

GND

GND

GND

Mode

0

R17

3.3V

GND

3

GND

4

Y2

6

Y1

7

INH

2

A

5

COM

1

VCC

8

SN74LVC2G53DCUR

U1

IOR

IOR_mcu

3.3V

3.3V

0.1µF

C4

GND

GND

Mode

0

R5

0

R40

DNP

GND

0

R4

0.1µF

C2

GND

10k

R28

10k

R2

10k

R7

GND

GND

TP12

GND

TP14

GND

TP15

GND

TP16

GND

TP17

GND

TP18

GND

TP11

GND

TP13

GND

GND

1

J8

1

J17

DIR HI = AtoB

DIR LOW = BtoA

DIR LOW = BtoA

GND

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15
17
19

21

23
25
27

16
18
20
22
24
26
28

J14

GND

4

B2

6

B1

7

DIR

5

A1

2

A2

3

VCCA

1

VCCB

8

SN74LVC2T45DCTR

U3

0

R29

DNP

33

R42

10.0k

R65

1

J6

5V INT

3.3V

INT

INT 5V

10.0k

R27

33

R85

TX_5V

TX_5V

TX

TX

RX

RX

RX_5V

RX_5V

10.0k

R63

1

2

Y1

RESET

1

GND

2

RESET

3

MR

4

VDD

5

TPS3125L30DBVR

U5

GND

MR

0

R39

RESET

3

2

1

Q1

D1

INT Indicator

120

R6

3.3V

INT

GND

3

2

1

Q2

GND

3

2

1

Q3

MR

GND

DTR

10k

R81

MR-RESET

820

R91

TXRDY

TXRDY 5V

RXRDY

RXRDY 5V

TP4

5V INT

TP1
TXRDY

CS

IOW

IOR_mcu

CS

IOW

IOR_mcu

CS
IOW
IOR_mcu

CS_5V
IOW_V
IOR_5V

CS_5V
IOW_V
IOR_5V

TP9

RX

100k

R57

RESET

VCC

10k

R112

VCC

VCC

10k

R111

10k

R106

10k

R113

10.0k

R114

GND

10.0k

R115

3.3V

120

R117

3.3V

GND

TXRDY

120

R116

3.3V

GND

RXRDY

D6

D8

3

1

2

Q5

3

2

1

Q4

TXRDY/RXRDY: When below trigger point, light turns on

10k

R118

GND

10k

R119

3.3V

1

2

3

J4

GND

1

2

3

J3

TXRDY

RXRDY

INT

D5

2

D6

3

D7

4

RX

7

TX

8

MODE

10

CS

11

A2

26

A1

27

A0

28

RXRDY

29

INT

30

OP

31

RTS

32

DTR

33

RESET

35

CTS

38

DSR

39

CD

40

RI

41

VCC

42

D0

43

D1

44

D2

45

D3

46

D4

47

XTAL1

14

XTAL2

15

IOW

16

VSS

18

IOR

19

TXRDY

23

NC

1

NC

5

NC

6

NC

9

NC

12

NC

25

NC

34

NC

36

NC

37

NC

48

NC

13

NC

17

NC

20

NC

21

NC

22

NC

24

TL16C750EPFB

U2

XTAL1

IOW

TX

RESET

RX

CTS

DSR

XTAL1

D7
D6

RXRDY

TXRDY

D5
D4
D3

D2

RTS

D1

D0

0

R120

DNP

OP

1

2

J9

1

2

J7

1

2

J15

1

2

J25

1

2

J21

LoopBack Enable

1

2

J24

1

2

J16

1

2

J19

1

2

J11

1uF

C7

1uF

C9

33pF

C10

33pF

C11

0

R1

0

R25

0

R30

0

R54

0

R60

0

R64

0

R72

0

R73

0

R75

0

R76

0

R78

0

R80

0

R90

0

R93

0

R94

0

R95

0

R96

0

R99

0

R100

0

R101

100k

R58

GND

3.3V

GND

1

2

3

J30

100k

R26

1

2
3

J31

INT

SH-J30

SH-J31

D0

D1

D2

D3

D4

D5

D6

D7

Schematic and Bill of Materials

www.ti.com

12

SLLU317 – January 2020

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Copyright © 2020, Texas Instruments Incorporated

TL16C750EEVM User's Guide

11

Schematic and Bill of Materials

11.1 Schematic

Figure 12. Schematic page 1

Summary of Contents for TL16C750EEVM

Page 1: ...EVM with the DUT at 3 3 V or lower 6 6 Loopback mode 7 7 Mode Select 9 8 Reset 10 9 Silkscreen Errors on EVM 10 10 Board Layout 11 11 Schematic and Bill of Materials 12 List of Figures 1 High to low s...

Page 2: ...EVM for evaluation 2 5 V Processor to 3 3 V VCC on TL16C750E The below sections describes how to set up the EVM when using a 5 V digital logic processor to interface with the TL16C750E used at a 3 3 V...

Page 3: ...slation Header denoted as J2 allows for the bidirectional data pins D0 D7 to be accessed The 5 V input pins RESET A0 A1 A2 CS IOW and IOR can be accessed at J22 The INT TXRDY and RXRDY lines each have...

Page 4: ...he expected voltage on the input power J26 is 5 V as this is a common processor voltage range a larger voltage should not be used The input voltage can be lower depending on VDO of the LDO this is out...

Page 5: ...oted on the EVM as U10 For the 3 3 V regulator to be selected to provide power to the TL16C750E and onboard level shifters J29 must be configured such that position 2 and position 3 are shunted togeth...

Page 6: ...ition 1 and 2 where the board denotes if VUART 3V6 J30 should be shunted from position 2 and 3 where the board denotes if VUART 3V6 Jumpers denoted as J9 J25 J29 J24 and J19 should not have shunts Fig...

Page 7: ...s INT TXRDY and RXRDY J12 allow access to the bidirectional data pins D0 D7 J14 are for the input pins RESET A0 A1 A2 CS IOW and IOR J18 provides access to the inputs RI CD DSR CTS and RX Finally J13...

Page 8: ...Loopback mode www ti com 8 SLLU317 January 2020 Submit Documentation Feedback Copyright 2020 Texas Instruments Incorporated TL16C750EEVM User s Guide Figure 7 Loopback mode...

Page 9: ...unted or shunted at position 2 and 3 the TL16C750E is in Intel mode This requires lines CS IOW and IOR to be used to read or write from the device If positions 1 and 2 are shunted on J1 Motorola mode...

Page 10: ...1 and 2 and J14 position 1 and 2 by toggling the logic level Driving the logic level low places the device in reset Alternatively a hardware reset switch is provided and denoted as S1 A reset is obse...

Page 11: ...w ti com Board Layout 11 SLLU317 January 2020 Submit Documentation Feedback Copyright 2020 Texas Instruments Incorporated TL16C750EEVM User s Guide 10 Board Layout Figure 10 EVM top Figure 11 EVM bott...

Page 12: ...0 1 F C3 50V 0 01 F C5 0 R56 0 R53 0 R59 DNP MR RESET MR RESET 30 R41 CD DSR CTS CD DSR CTS CD_5V DSR_5V CTS_5V CD_5V DSR_5V CTS_5V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 J2 D0_5V D1_5V D2_5V D3_5V D4...

Page 13: ...01uF C22 25V 0 1uF C21 D5 Iout MAX 150mA 1 2 3 J29 3 3V 0 R110 DNP LDO OUT VCC D7 J10 VUART 3 3V 0 R108 SH J29 www ti com Schematic and Bill of Materials 13 SLLU317 January 2020 Submit Documentation F...

Page 14: ...CAP CERM 0 01 uF 25 V 5 C0G NP0 0603 0603 C0603H103J3GACTU Kemet C23 1 2 2uF CAP CERM 2 2 uF 16 V 10 X5R 0805 0805 EMK212BJ225KG T Taiyo Yuden D1 D4 2 Yellow LED Yellow SMD LED 1 3x0 65x0 8mm LY L29K...

Page 15: ...MOSFET N CH 50 V 0 2 A SOT 23 SOT 23 RUC002N05T116 Rohm None Q5 1 8V MOSFET P CH 8 V 5 3 A SOT 23 SOT 23 Si2329DS Vishay Semiconductor None R1 R25 R30 R54 R60 R64 R72 R73 R75 R76 R78 R80 R90 R93 R94...

Page 16: ...llow Multipurpose Testpoint 5014 Keystone TP4 TP5 2 Test Point Multipurpose White TH White Multipurpose Testpoint 5012 Keystone TP6 1 Test Point Multipurpose Orange TH Orange Multipurpose Testpoint 50...

Page 17: ...Bus Transceiver with Configurable Voltage Level Shifting and Three State Outputs DW0024A SOIC 24 DW0024A SN74LVC8T245DWR Texas Instruments Texas Instruments U10 1 150 mA 6 5 V 1 uA IQ Voltage Regulato...

Page 18: ...ther than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control tec...

Page 19: ...These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not in...

Page 20: ...instructions set forth by Radio Law of Japan which includes but is not limited to the instructions below with respect to EVMs which for the avoidance of doubt are stated strictly for convenience and s...

Page 21: ...any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electr...

Page 22: ...R DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthe...

Page 23: ...e resources are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reprod...

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