Strap Pin
R
L
Strap Pin
R
h
V
DD
Pull-Down
Pull-Up
Strap Pin
R
L
Strap Pin
R
h
V
DD
Level 1
Level 2/3
R
L
Strap Pin
R
h
V
DD
Level 4
System Overview
10
TIDUES1A – October 2019 – Revised February 2020
Copyright © 2019–2020, Texas Instruments Incorporated
EMC Compliant 10/100-Mbps Ethernet PHY Reference Design With IEEE
802.3at Type-1 (
≤
12.95 W) PoE-PD
Figure 3. Four-Level Bootstrap Configuration (DP83822I)
Figure 4. Two-Level Booststrap Configuration (DP83825I)
All the strap pins have the provision for populating the strap resistors for Ethernet PHYs on both PSE and
PD side boards to place the device in to a specific configuration as desired.
2.4.3.1
Hardware Bootstrap Configuration on PSE Side Board
On the PSE side board, two Ethernet PHYs (DP83822I and DP83825I) shares the common serial
management bus. To distinguish between the PHYs, each PHY must have a unique PHY address. The
PHY address is latched into the device upon power up or hardware reset. The DP83822I device can be
configured for any of the 32 possible PHY addresses available through bootstrap configuration. The
DP83822I device supports PHY address strapping values 0x0000 (0b00000) through 0x001F (0b11111).
By default, the DP83822I device will latch-in the PHY address 0x0001 (0b00001). The DP83825I device
can be configured for up to 4 PHY addresses available through bootstrap configuration. By default, the
DP83822I will latch-in PHY address 0x00 (0b00). The PHY address can be changed by adding the pullup
or pulldown resistors as recommended by the device data sheet. In this reference design system, the
default PHY addresses are used simply because both PHYs latch-in different PHY addresses upon power
up or hardware reset.
Both Ethernet PHYs (DP83825I and DP83822I) offer two types of RMII operations: RMII Slave and RMII
Master. In RMII Slave operation, the PHY operates off of a 50-MHz CMOS-level oscillator connected to
the XI pin and shares the same clock as the MAC. In RMII Master operation, the PHY operates off of
either a 25-MHz CMOS-level oscillator connected to XI pin or a 25-MHz crystal connected across XI and
XO pins. In this reference design, the DP83825I device is configured as RMII master and the DP83822I
device as RMII slave. In RMII master mode, the DP83825I device operates off of a 25-MHz crystal
connected across XI and XO pins. In RMII Slave operation, the DP83822I device operates off of a 50-MHz
reference clock output from the DP83825I device connected to the XI pin. By default, the DP83825I device
