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Texas Instruments ThunderSWITCH II TNETX4090, User Manual

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TNETX4090

ThunderSWITCH II

9-PORT 100-/1000-MBIT/S ETHERNET

 SWITCH

 

 

SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999

1

POST OFFICE BOX 655303 

•

 DALLAS, TEXAS 75265

D

Single-Chip 100-/1000-Mbit/s Device

D

Integrated Physical Coding Sublayer (PCS)
Logic Provides Direct Interface to Gigabit
Transceivers

D

Integrated Address-Lookup Engine and
Table Memory for 2-K Addresses

D

Supports IEEE Std 802.1Q Virtual-LAN
(VLAN) Tagging Scheme

D

Provides Data Path for Network
Management Information [No External
Media-Access Control (MAC) Required]

D

Full-Duplex IEEE Std 802.3 Flow Control

D

Half-Duplex Back-Pressure Flow Control

D

Fully Nonblocking Architecture Using
High-Bandwidth Rambus Memory

D

Simple Expansion Via the Gigabit Interface
for Higher-Density Port Solutions

D

Port Trunking/Load Sharing for
High-Bandwidth Interswitch Links

D

Supports Pretag Extended Port Awareness

D

EEPROM Interface for Autoconfiguration
(No CPU Required for Nonmanaged Switch)

D

Provides Direct Input/Output (DIO) Interface
for Configuration and Statistics Information

D

Supports On-Chip Per-Port Storage for
Etherstat

 and Remote Monitoring (RMON)

Management Information Bases (MIBs)

D

Fabricated in 2.5-/3.3-V Low-Voltage
Technology

D

Supports Ring-Cascade Mode

D

Supports Spanning Tree

D

Packaged in 352-Terminal Ball Grid Array
Package

description

The TNETX4090 is a 9-port 100-/1000-Mbit/s nonblocking Ethernet

 switch with an on-chip address-lookup

engine. The TNETX4090 provides a low-cost, high-performance switch solution. The TNETX4090 is a fully
manageable desktop switch solution achieved by combining the TNETX4090 with physical interfaces and
high-bandwidth rambus-based packet memory and a CPU. The TNETX4090 also provides an interface capable
of receiving and transmitting simple-network management protocol (SNMP) and bridge protocol data units
(BPDU) (spanning tree) frames.

The TNETX4090 provides eight 10-/100-Mbit/s interfaces and one 100-/1000-Mbit/s interface. In half-duplex
mode, all ports support back-pressure flow control to reduce the risk of data loss for a long burst of activity. In
the full-duplex mode of operation, the device uses IEEE Std 802.3 frame-based flow control. With full-duplex
capability, ports 0–7 support 200-Mbit/s aggregate bandwidth connections. Port 8 supports 2 Gbit/s to desktops,
high-speed servers, hubs, or other switches in the full-duplex mode. The physical coding sublayer (PCS)
function is integrated on chip to provide a direct 10-bit interface to the gigabit Ethernet transceiver. The
TNETX4090 also supports port trunking/load sharing on the 10-/100-Mbit ports. This can be used to group ports
on interswitch links to increase the effective bandwidth between the systems. In the ring-cascade mode, port 8
can be used to connect multiple devices in a ring topology, which provides a low-cost, high-port-density desktop
switch. Pretagging and extended port awareness allow the TNETX4090 to be used as a front end to a router
or crossbar switch to build a cost-effective, high-density, high-performance system.

The internal address-lookup engine (IALE) supports up to 2-K unicast/multicast and broadcast addresses and
up to 64 IEEE Std 802.1Q VLANs. For interoperability, each port can be programmed as an access port or
non-access port to recognize VLAN tags and transmit frames with VLAN tags to other systems that support
VLAN tagging. The IALE performs destination- and source-address comparisons and forwards unknown
source- and destination-address packets to ports specified via programmable masks.

Copyright 

 1998, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TI, ThunderSWITCH, and ThunderSWITCH II are trademarks of Texas Instruments Incorporated.
Ethernet and Etherstat are trademarks of Xerox Corporation.
Secure Fast Switching is a trademark of Cabletron Systems, Inc.
Port-trunking and load-sharing algorithms were contributed by Cabletron Systems, Inc. and are derived from, and compatible with, Secure Fast
Switching

.

Summary of Contents for ThunderSWITCH II TNETX4090

Page 1: ...plex mode of operation the device uses IEEE Std 802 3 frame based flow control With full duplex capability ports 0 7 support 200 Mbit s aggregate bandwidth connections Port 8 supports 2 Gbit s to desktops high speed servers hubs or other switches in the full duplex mode The physical coding sublayer PCS function is integrated on chip to provide a direct 10 bit interface to the gigabit Ethernet tran...

Page 2: ...atistics counters is provided via the direct input output DIO interface Management frames can be received and transmitted via the DIO interface creating a complete network management solution Figure 1 is a block diagram of the TNETX4090 The TNETX4090 memory solution combines low cost and extremely high bandwidth using 600 Mbit pin s concurrent RDRAM The packet memory has been implemented to maximi...

Page 3: ...ation 73 Mechanical Data 76 Description 1 Terminal Functions 7 DIO Interface Description 18 Receiving Transmitting Management Frames 27 State of DIO Signal Terminals During Hardware Reset 28 IEEE Std 802 1Q VLAN Tags on the NM Port 28 Frame Format on the NM Port 28 Full Duplex NM Port 31 NM Bandwidth and Priority 31 Interrupt Processing 31 PHY Management Interface 31 MAC Interface 32 Receive Contr...

Page 4: ...THERNET SWITCH SPWS044E DECEMBER 1997 REVISED AUGUST 1999 4 POST OFFICE BOX 655303 DALLAS TEXAS 75265 GGP PACKAGE BOTTOM VIEW A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 26 24 22 20 18 16 14 12 10 8 6 4 2 25 23 21 19 17 15 13 11 9 7 5 3 1 ...

Page 5: ... M03_RCLK M03_RENEG M03_RXD0 M03_RXD1 M03_RXD2 M03_RXD3 M03_RXDV M03_RXER M03_TCLK M03_TXD0 M03_TXD1 M03_TXD2 M03_TXD3 M03_TXEN M03_TXER M04_COL M04_CRS M04_LINK M04_RCLK M04_RENEG M04_RXD0 M04_RXD1 M04_RXD2 M04_RXD3 M04_RXDV M04_RXER M04_TCLK M04_TXD0 M04_TXD1 M04_TXD2 M04_TXD3 M04_TXEN M04_TXER M05_COL M05_CRS M05_LINK M05_RCLK M05_RENEG M05_RXD0 M05_RXD1 M05_RXD2 M05_RXD3 M05_RXDV M05_RXER M05_...

Page 6: ...ATA6 SDATA7 M23 AF22 AE22 AD22 AF20 AE20 AD20 AC20 AF21 AE21 AD21 AC21 SDMA SINT SRDY SRNW SRXRDY STXRDY TCLK TDI TDO TMS TRST VDD 2 5 AF24 AF19 AF23 AC22 AE23 AD23 L24 M24 L23 M25 L25 B2 VDD 2 5 VDD 2 5 VDD 2 5 VDD 2 5 VDD 2 5 VDD 2 5 VDD 2 5 VDD 2 5 VDD 2 5 VDD 2 5 VDD 2 5 VDD 2 5 B25 C3 C24 D4 D9 D14 D18 D23 J4 J23 N4 P23 VDD 2 5 VDD 2 5 VDD 2 5 VDD 2 5 VDD 2 5 VDD 2 5 VDD 2 5 VDD 2 5 VDD 2 5 V...

Page 7: ... or pulldowns are required in their systems control logic interface TERMINAL I O DESCRIPTION NAME NO I O DESCRIPTION RESET M23 I Device reset Asserted for a minimum of 100 µs after power supplies and clocks have stabilized The system clock must be operational during reset FLOW AF8 O Flow control When flow control is activated flow in SysControl 1 and the number of free external memory buffers is b...

Page 8: ...ong as initd in SysControl 0 regardless of the state of M08_LINK M08_RCLK I Pullup Receive clock Receive clock source from the attached PHY M08_RFCLK I Pullup Reference clock Reference clock used as the clock source for the transmit side of this port and to generate M08_GTCLK M08_RXD7 M08_RXD6 M08_RXD5 M08_RXD4 M08_RXD3 M08_RXD2 M08_RXD1 M08_RXD0 I Pullup Receive data Byte receive data from the at...

Page 9: ...8_RFCLK I Pullup Reference clock Reference clock used as the clock source for the transmit side of this port and to generate M08_GTCLK M08_RFCLK provides the clock source for the entire internal PCS sublayer M08_RXD7 M08_RXD6 M08_RXD5 M08_RXD4 M08_RXD3 M08_RXD2 M08_RXD1 M08_RXD0 I Pullup Receive data Least significant eight bits of the 10 bit receive code group Even numbered code groups are latche...

Page 10: ...f M08_LINK M08_RCLK I Pullup Receive clock Receive clock source from the attached PHY or PMI device M08_RFCLK I Pullup Transmit clock Transmit clock from the attached PHY or PMI device M08_RXD7 M08_RXD6 I Pullup Unused These terminals can be left unconnected M08_RXD5 I O Pullup IEEE Std 802 3x pause frame support selection If pulled low either internally or by the attached PHY or PMI device M08_RX...

Page 11: ...ISTOR DESCRIPTION M00_COL M01_COL M02_COL M03_COL M04_COL M05_COL M06_COL M07_COL C21 D16 C11 A6 H2 N2 V1 AC6 I Pulldown Collision sense Assertion of Mxx_COL indicates network collision In full duplex mode the port does not start transmitting a new frame if this signal is active the value of this terminal is ignored at all other times M00_CRS M01_CRS M02_CRS M03_CRS M04_CRS M05_CRS M06_CRS M07_CRS...

Page 12: ...1_RXD1 M01_RXD0 M02_RXD3 M02_RXD2 M02_RXD1 M02_RXD0 M03_RXD3 M03_RXD2 M03_RXD1 M03_RXD0 M04_RXD3 M04_RXD2 M04_RXD1 M04_RXD0 M05_RXD3 M05_RXD2 M05_RXD1 M05_RXD0 M06_RXD3 M06_RXD2 M06_RXD1 M06_RXD0 M07_RXD3 M07_RXD2 M07_RXD1 M07_RXD0 D20 C20 B20 A20 D15 C15 B15 A15 D10 C10 B10 A10 D5 C5 B5 A5 K3 K2 K1 J1 R4 R3 R2 R1 Y4 Y3 Y2 Y1 AC7 AD7 AE7 AF7 I Pullup Receive data Nibble receive data from the attac...

Page 13: ...2_TXD2 M02_TXD1 M02_TXD0 M03_TXD3 M03_TXD2 M03_TXD1 M03_TXD0 M04_TXD3 M04_TXD2 M04_TXD1 M04_TXD0 M05_TXD3 M05_TXD2 M05_TXD1 M05_TXD0 M06_TXD3 M06_TXD2 M06_TXD1 M06_TXD0 M07_TXD3 M07_TXD2 M07_TXD1 M07_TXD0 C22 B22 A22 A23 C18 B18 A18 A19 D12 C12 B12 A12 D7 C7 B7 A7 G4 G3 G2 G1 M4 M3 M2 M1 U4 U3 U2 U1 AC5 AD5 AE5 AF5 O None Transmit data Byte transmit data When Mxx_TXEN is asserted these signals car...

Page 14: ...11 C8 H3 N3 V2 AF4 O None Transmiterror Allows coding errors to be propagated across the MII Mxx_TXER is asserted at the end of an under running frame enabling the TNETX4090 to force a coding error MII management interface TERMINAL I O INTERNAL DESCRIPTION NAME NO I O RESISTOR DESCRIPTION MDCLK K26 O Pullup Serial MII management data clock Disabled high impedance Z state through the use of the ser...

Page 15: ... and read data packets The request packet contains the address operation codes and other control information These are RSL signals see Note 1 DBUS_EN T25 O None Bus enable Controls signal to transfer column addresses for random access nonsequential transactions This is an RSL signal see Note 1 DCCTRL P24 I None Current control program Connected to the current control resistor whose other terminal ...

Page 16: ...provided SINT AF19 O None Interrupt Interrupt to the attached microprocessor The interrupt type can be found in the Int register SRDY AF23 O Pullup DIO ready When low during reads SRDY indicates to the host when data is valid to be read When low during writes SRDY indicates when data has been received SRDY is driven high for one clock cycle before placing the output in high impedance after SCS is ...

Page 17: ...low if the port is configured for full duplex operation It is high at all other times power supply TERMINAL DESCRIPTION NAME NO DESCRIPTION GND A1 A2 A13 A14 A25 A26 AF13 AF14 B1 B3 B24 B26 C2 C25 N1 N26 P1 P25 P26 R23 R24 R26 T24 U23 W23 W24 W25 W26 Y23 Y25 AA23 AA25 AB25 AD2 AD25 AE1 AE3 AE24 AE26 AF1 AF2 AF25 AF26 Ground The 0 V reference for the TNETX4090 GNDa U24 Ground The 0 V reference for ...

Page 18: ...cription of registers Table 2 DIO Internal Register Address Map BYTE 3 BYTE 2 BYTE 1 BYTE 0 DIO ADDRESS Port1Control Port0Control 0x0000 Port3Control Port2Control 0x0004 Port5Control Port4Control 0x0008 Port7Control Port6Control 0x000C Reserved Port8Control 0x0010 Reserved 0x0014 0x003C Reserved UnkVLANPort MirrorPort UplinkPort 0x0040 Reserved AgingThreshold 0x0044 Reserved 0x0048 0x004C NLearnPo...

Page 19: ...x0118 VLAN7Ports 0x011C VLAN8Ports 0x0120 VLAN9Ports 0x0124 VLAN10Ports 0x0128 VLAN11Ports 0x012C VLAN12Ports 0x0130 VLAN13Ports 0x0134 VLAN14Ports 0x0138 VLAN15Ports 0x013C VLAN16Ports 0x0140 VLAN17Ports 0x0144 VLAN18Ports 0x0148 VLAN19Ports 0x014C VLAN20Ports 0x0150 VLAN21Ports 0x0154 VLAN22Ports 0x0158 VLAN23Ports 0x015C VLAN24Ports 0x0160 VLAN25Ports 0x0164 VLAN26Ports 0x0168 VLAN27Ports 0x016...

Page 20: ...Ports 0x01D4 VLAN54Ports 0x01D8 VLAN55Ports 0x01DC VLAN56Ports 0x01E0 VLAN57Ports 0x01E4 VLAN58Ports 0x01E8 VLAN59Ports 0x01EC VLAN60Ports 0x01F0 VLAN61Ports 0x01F4 VLAN62Ports 0x01F8 VLAN63Ports 0x01FC Reserved 0x0200 0x02FC VLAN1QID VLAN0QID 0x0300 VLAN3QID VLAN2QID 0x0304 VLAN5QID VLAN4QID 0x0308 VLAN7QID VLAN6QID 0x030C VLAN9QID VLAN8QID 0x0310 VLAN11QID VLAN10QID 0x0314 VLAN13QID VLAN12QID 0x...

Page 21: ...ved Port8QTag 0x0390 Reserved 0x0394 0x03FC Port1Status Port0Status 0x0400 Port3Status Port2Status 0x0404 Port5Status Port4Status 0x0408 Port7Status Port6Status 0x040C Reserved Port8Status 0x0410 Reserved 0x0414 0x043C FindNode 23 16 FindNode 31 24 FindNode 39 32 FindNode 47 40 0x0440 FindVLAN FindControl FindNode 7 0 FindNode 15 8 0x0444 FindPort 0x0448 NewNode 23 16 NewNode 31 24 NewNode 39 32 N...

Page 22: ...roup29 0x0574 XMultiGroup30 0x0578 XMultiGroup31 0x057C XMultiGroup32 0x0580 XMultiGroup33 0x0584 XMultiGroup34 0x0588 XMultiGroup35 0x058C XMultiGroup36 0x0590 XMultiGroup37 0x0594 XMultiGroup38 0x0598 XMultiGroup39 0x059C XMultiGroup40 0x05A0 XMultiGroup41 0x05A4 XMultiGroup42 0x05A8 XMultiGroup43 0x05AC XMultiGroup44 0x05B0 XMultiGroup45 0x05B4 XMultiGroup46 0x05B8 XMultiGroup47 0x05BC XMultiGr...

Page 23: ...rol 0x0700 Reserved 0x0704 PCS8ANLinkP PCS8ANAdvert 0x0708 PCS8ANNxt PCS8ANExp 0x070C Reserved PCS8ANLinkPNxt 0x0710 Reserved 0x0714 0x0718 PCS8ExStatus Reserved 0x071C Reserved 0x0720 0x07FC Reserved DMAAddress 0x0800 Reserved Int 0x0804 Reserved IntEnable 0x0808 SysTest FreeStackLength 0x080C RAMAddress 0x0810 Reserved RAMData 0x0814 Reserved NMRxControl 0x0818 Reserved NMTxControl 0x081C Reserv...

Page 24: ...ach statistic is four bytes long To determine the address of a particular statistic replace the xx in the head column with the characters from the tail address Table 3 has two tail columns one for even numbered ports and the other for odd numbered ports See the TNETX4090 Programmer s Reference Guide literature number SPAU003 for a detailed description of the statistic registers Example Port 7 head...

Page 25: ... 28 A8 0x85xx 65 127 octet frames 2C AC 0x86xx 128 255 octet frames 30 B0 0x86xx 256 511 octet frames 34 B4 0x87xx 512 1023 octet frames 38 B8 0x87xx 1024 1518 octet frames 3C BC 0x88xx Net octets 40 C0 0x88xx SQE test errors 44 C4 0x89xx Tx octets 48 C8 0x89xx Good transmit frames 4C CC Reserved 0x8Axx Single collision transmit frames 50 D0 Reserved 0x8Axx Multiple collision transmit frames 54 D4...

Page 26: ...0x900x Pause transmit frames 0 1 0x901x Pause receive frames 4 2 0x902x Security violations 8 3 0x903x Reserved C 4 0x904x 5 0x905x 6 0x906x 7 0x907x 8 0x908x NM 0x909x 0x90Ax 0x90Bx 0x90Cx 0x90Dx 0x90Ex 0x90Fx 0x910x 0x911x 0x912x 0x913x Reserved 0x914x Reserved 0x915x 0x916x 0x917x 0x918x 0x919x 0x91Ax 0x91Bx 0x91Cx 0x91Dx 0x91Ex 0x91Fx The NM port does not have this statistic This address is re...

Page 27: ...anagement frames Frames originating within the host are written to the NM port via the NMRxControl and NMData registers Once a frame has been fully written it is then received by the switch and routed to the destination port s Frames that were routed to this port from any of the switch ports are placed in a queue until the host is ready to read them via the NMTxControl and NMData registers They th...

Page 28: ...tes are a valid tag under all other circumstances When a frame is transmitted by the NM port received by the host no tag stripping occurs so the frame may contain one or possibly two tags depending on how the frame originally was received frame format on the NM port The frame format on the NM port differs slightly from a standard Ethernet frame format The key differences are the frame always conta...

Page 29: ...rctype also is 0 if the frame VLAN ID was 0x000 and was replaced by the port VLANID PVID from the PortxQTag register In an IEEE Std 802 1D compliant application the header simply can be removed from the frame to produce a headerless frame with a correct CRC word All other bits in the byte are reserved and are 0 The second TPID byte output contains D Odd parity protection bits for the other three b...

Page 30: ...he host via the NM port are required to contain a valid IEEE Std 802 1Q VLAN ID in the third and fourth bytes following the source address the NM port does not have a PortxQTag register for inserting a VLAN tag if none is provided and does not have an rxacc bit Frames that do not contain a VLAN tag are incorrectly routed They also can be corrupted at the transmission port s The header stripping pr...

Page 31: ...x interrupt are set when the receive FIFO is completely empty This indicates that the NM port is ready to accept a frame of any length up to 1535 bytes If the host wished to download a sequence of frames it could use the freebuffs field to determine space availability PHY management interface This interface gives the user an easy way to implement a software controlled bit serial MII PHY management...

Page 32: ... should be recorded short frames All received frames shorter than 64 bytes are discarded upon reception and are not stored in memory or transmitted receive filtering of frames Received frames that contain an error e g CRC alignment jabber etc are discarded before transmission and the relevant statistics counter is updated data transmission The MAC takes data from the TNETX4090 internal buffer memo...

Page 33: ...cement The measurement reference for the interpacket gap of 96 bit times is changed depending on frame traffic conditions If a frame is successfully transmitted without collision 96 bit times is measured from Mxx_TXEN If the frame suffered a collision 96 bit times is measured from Mxx_CRS backoff The device implements the IEEE Std 802 3 binary exponential backoff algorithm receive versus transmit ...

Page 34: ... 100 Mbit s required This signal reflects the inverse of the value of req10 in the appropriate PortxControl register Mxx_TD3 does not take part in the negotiation process and outputs as 0 while Mxx_LINK is low As long as Mxx_LINK is low the PHY outputs on D Mxx_RXD0 is the result of duplex negotiation 0 half 1 full that is recorded in the duplex bit of the appropriate PortxStatus register D Mxx_RX...

Page 35: ...ÎÎÎÎ ÎÎÎÎ Reserved Reserved Reserved Reserved Reserved Reserved Pause Reserved Speed Reserved Duplex Reserved Reserved Pause Speed Duplex 1200 ms Min 750 ms Min 80 ms Min Link Fail or Renegotiate Autonegotiate Page Swap Commences Autonegotiate Page Swap Completes Autonegotiate Complete and Link Good TXCLK TXEN TXER TXD3 TXD2 TXD1 TXD0 LINK RXCLK RXDV RXER RXD3 RXD2 RXD1 RXD0 Figure 3 10 100 Mbit s...

Page 36: ...in PCS8Control Figure 4 shows how the gigabit port on the TNETX4090 can be connected to a SERDES device Table 1 gives a description of the device terminals M08_RXD0 M08_RXD7 Tie to Signal Detect Terminal of Optical Receiver SERDES Device or to VCC Serial Data Output Serial Data Input M08_TXD0 M08_TXD7 M08_TXEN M08_TXER TD0 TD7 TD8 TD9 SYNC NC VCC SYNCEN M08_EWRAP M08_LINK TNETX4090 Gigabit Port Te...

Page 37: ...gnals is such that the higher performance option is represented by a value of 1 so if the MAC does not require the higher performance or the PHY cannot supply it either can pull the signal low forcing the port to use the lower performance option The status of the link for this port is indicated on M08_LINK and is observable in Port8Status M08_LINK plays no part in the negotiation of pause or duple...

Page 38: ...indicating the ports on this TNETX4090 for which the frame is destined The information contained within these tags also enables the TNETX4090 to be incorporated in a system where routing decisions are made at a higher level Use of pretagging is enabled by setting pretag in the appropriate PortxControl register pretag on transmission Port 8 provides the frame source port and crossbar matrix destina...

Page 39: ... pretag takes the form of a 32 bit value divided into eight nibbles with each nibble being replicated on M08_RXD3 M08_RXD0 and M08_RXD7 M08_RXD4 This replaces the preamble and sof delimiter normally received at this time Figure 6 shows the timing relationship and Table 11 and Table 12 show the fields within the tag for learning and directed format respectively ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ...

Page 40: ...or port n on this device ring cascade topology The ringports register allows port 8 to be used to cascade multiple TNETX4090 devices using a full duplex ring cascade topology see Figure 7 TNETX4090 0 1 2 3 4 5 6 7 Port 8 RXD FLOW COL TXD TNETX4090 0 1 2 3 4 5 6 7 Port 8 RXD FLOW COL TXD TNETX4090 0 1 2 3 4 5 6 7 Port 8 RXD FLOW COL TXD Figure 7 Ring Cascade Topology This configuration provides a w...

Page 41: ... identifies a frame that originated at this device and that has passed completely around the ring The pretag format is shown in Figure 8 ÎÎÎÎ ÎÎÎÎ Ring ID Preamble M08_TXD3 M08_TXD0 M08_RXD3 M08_RXD0 M08_TXEN M08_RXDV M08_GTCLK ÎÎÎÎ ÎÎÎÎ Ring ID Preamble M08_TXD7 M08_TXD4 M08_RXD7 M08_RXD4 Figure 8 Ring Topology Pretag Timing The devices in the ring are connected as shown in Table 13 Table 13 Ring...

Page 42: ...device can be used Both use a two wire serial interface for communication and are available in a small footprint package D The 24C02 provides 2048 bits organized as 256 8 Downloading data from the EEPROM initializes DIO addresses 0x0000 through 0x00FB These registers control all initializable functions except VLANs The downloading sequence starts with DIO address 0x0000 continuing in ascending ord...

Page 43: ...s 0x00FC 0x00FF just above SysControl As each byte is loaded from the EEPROM the bits within that byte are entered into the CRC checker bit wise most significant bit first A valid CRC always must be provided by the EEPROM The EEPROM data for the most significant bit of SysControl is withheld until the CRC computed by the device has been checked against the one read from the EEPROM If the CRC is in...

Page 44: ...Y No link Off Link but no activity On Activity Flashing at 8 Hz Port 08 has an additional LED C08 to indicate the occurrence of a collision when operating in PMA mode this LED also has three states as shown in Table 16 Table 16 Collision LED States STATE DISPLAY No collision or non PMA mode Off Occasional collision On Frequent collisions Flashing at 8 Hz The interface is intended for use in conjun...

Page 45: ...LED in LEDControl has been set The CRC and parity error indications are cleared by hardware reset terminal or DIO The CRC error indication also is cleared by setting load to 1 The parity error indication also is cleared by setting start to 1 lamp test When the device is in the hardware reset state LED_DATA is driven low and LED_CLK runs continuously This causes all LEDs to be illuminated and serve...

Page 46: ... DRX_CLK DTX_CLK BUS_CLK TXCLK RXCLK BUS ENABLE BUS CTRL BUS DATA 8 0 Concurrent RDRAM 5 13 VREF VDD GND SIN SOUT TXCLK RXCLK BUS ENABLE BUS CTRL BUS DATA 8 0 Concurrent RDRAM 5 13 VREF VDD GND SIN SOUT TXCLK RXCLK BUS ENABLE BUS CTRL BUS DATA 8 0 Concurrent RDRAM 5 13 VREF VDD GND SIN SOUT VCC NC SCHAIN15 SCHAIN1 SCHAIN0 Clock Source NC No internal connection Figure 10 Multiple RDRAM Module Conne...

Page 47: ...ELOAD 000001 Optional IDCODE 000100 Optional HIGHZ 000101 Optional RACBIST 000110 Private TI testing Others Mandatory BYPASS 111111 HIGHZ instruction When selected the HIGHZ instruction causes all outputs and bidirectional terminals to become high impedance All pullup and pulldown resistors are disabled RACBIST instruction The RACBIST instruction invokes a built in self test of the RAC and the ram...

Page 48: ...Header Stripped Header Retained VLANnQID VLAN ID Lookup Source Address SA Destination Address DA Reset 1st Location 0x001 All Others 0x000 No Match VLAN and Ethernet Addresses VLAN ADDR Reset to All 0s SA DA VLAN VLAN Index Frame Routing Algorithm UnkUniPorts UnkMultiPorts UnkSrcPorts UnkVLANPort TxBlockPorts RxUniBlockPorts RxMultiBlockPorts MirrorPort UplinkPort TrunkMapx TrunkxPorts NLearnPorts...

Page 49: ...ember The IALE checks to see if the source port already has been declared as a member of this VLAN If not an interrupt is provided to allow the attached CPU to add this port as a new member of the VLAN IEEE Std 802 1Q header transmission The IEEE Std 802 1Q header is carried within the frame to the transmitting MAC port where the decision to strip out the header before transmission is made based o...

Page 50: ...f the table is full and a new address must be added to the table In this mode the age stamp for the addresses is not refreshed frame routing determination When a frame is received its 48 bit destination and source addresses are extracted and the VLAN index is determined as described in VLAN Support The destination address and VLAN index are then looked up in the IALE records to determine if they e...

Page 51: ...rt Blocked by RxMultiBlockPorts and Dest Nblck 0 Source Port Blocked by RxMultiBlockPorts Yes Source Port Blocked by RxUniBlockPorts Destination is Multicast Yes Yes Source Port Blocked by RxMultiBlockPorts or UnkVLAN 0 No No No No No No Port Routing Code Port Code From Records Port Routing Code Port Vector From Records Port Routing Code UnkMultiPorts Port Routing Code UnkUniPorts Port Routing Cod...

Page 52: ...t and other trunk members From Port Routing Code Source Address Found Source Port 1 in NLearnPorts No AND UnkSrcPorts With VLAN VLANnPorts Then OR With Port Routing Code Yes No Source Locked Bit 1 Yes Source Port Moved Source Secure Bit 1 No secvio Yes Yes Discard Frame chng No To C Continued No Yes Stayed Within a Trunk Yes Source Port 1 in RingPorts No Yes Unknown Source Figure 12 Frame Routing ...

Page 53: ...ithm see Note A Destination Found Yes No Port Routing Code is Adjusted by Load Sharing Algorithm see Note A Yes NOTE A See Port Trunking Load Sharing Port Routing Code 0 Send Frame to Ports Indicated by Port Routing Code No Yes Discard Frame D C Figure 12 Frame Routing Algorithm Continued port routing code The IALE creates a port routing code in which each bit marked with a 1 represents a potentia...

Page 54: ... of a trunk group are software configurable via the DIO interface Trunk port determination is the final step in the IALE frame routing algorithm Once the destination port s for a frame have been determined the port routing code is examined to see if any of the destination port s are members of a trunk If so the trunking algorithm is applied to select the port within the trunk that transmits the fr...

Page 55: ...nsures that packets do not get disordered on the trunk ports Note that since port 4 is not a member of any port trunk group all the entries for this port have been set to 1 In fact functionally this can be thought of as a single port trunk Table 23 TrunkMapx Register Settings for Traffic Distribution on Trunk Groups 0 and 1 MAP TRUNK PORT INDEX 7 6 5 4 3 2 1 0 0 0 1 0 1 0 0 1 0 1 0 0 0 1 1 1 0 0 2...

Page 56: ...reshold should be set so that all ports can complete reception of a maximum size frame that is each port should have enough time to activate the flow mechanisms without dumping a frame for which reception has started D If holb 1 back pressure is applied as when holb 0 or to an individual port when the buffers held in memory for data that arrived on that port is greater than the available pool rema...

Page 57: ...he test for buffer use controlled by the holb bit in SysControl into the action of the FLOW terminal FLOW goes high if either the number of buffers left is less than the FlowThreshold value or a ring mode port receive operation has exceeded its fair share of buffers Setting holbrm 1 makes FLOW respond only to FlowThreshold value violations system test capabilities RDRAM The external RDRAM can be r...

Page 58: ...me to be forwarded from one port to another in this fashion the switch must be programmed as follows D Assign a unique VID to each of the PortxQTag registers and program these tags into the VLANnQID registers D The VLANnPorts register associated with each of the VLANnQID registers should have only one bit set indicating to which port frames containing that IEEE Std 802 3 tag should be routed D Rxa...

Page 59: ... to be verified Any port can be the source port not just the NM port as shown in Figure 14 By using multicast broadcast frames traffic can be routed selectively between ports involved in the test or return the frame directly before retransmission on the uplink Software control of the external PHYs is required to configure them for loopback If the internal PCS is in use port configured in PMA mode ...

Page 60: ...gs can cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods can affect device reliability NOTE 1 All voltage values are with respect to GND recommended operating conditio...

Page 61: ...input current VI VIH 1 µA IIL Low level input current VI VIL 1 µA VOHR High level output voltage RSL IOH 2 VDD V VOLR Low level output voltage RSL 0 0 4 V IDD 2 5V VDD 2 5V max DTX_CLK and DRX_CLKf 83 33 MHz 1 5 IDD 3 3V Supply current VDD 3 3V max DTX_CLK and DRX_CLKf 83 33 MHz 0 5 A IDD 2 5 VDD 2 5 max DTX_CLK and DRX_CLKf 83 33 MHz 0 175 Ci Capacitance input 6 pF Co Capacitance output 6 pF timi...

Page 62: ...LK COL 2 5 ns 5 th Mxx_RXD Hold time Mxx_RXD7 Mxx_RXD0 valid after Mxx_RCLK COL 1 5 ns 5 th Mxx_RXDV Hold time Mxx_RXDV valid after Mxx_RCLK COL 1 5 ns 5 th Mxx_RXER Hold time Mxx_RXER valid after Mxx_RCLK COL 1 5 ns 6 tskew Mxx_RBC Skew between receive byte clock 1 and receive byte clock 0 7 5 8 5 ns tdrift is the minimum time for either RBC0 or RBC1 to drift from 63 5 MHz to 64 5 MHz or 60 Mhz t...

Page 63: ..._TXD Setup time Mxx_RXD7 Mxx_RXD0 valid before Mxx_GTCLK 2 ns 4 tsu Mxx_TXEN Setup time Mxx_RXDV valid before Mxx_GTCLK 2 ns 4 tsu Mxx_TXER Setup time Mxx_RXER valid before Mxx_GTCLK 2 ns 5 th Mxx_TXD Hold time Mxx_RXD7 Mxx_RXD0 valid after Mxx_GTCLK 1 ns 5 th Mxx_TXDV Hold time Mxx_RXDV valid after Mxx_GTCLK 1 ns 5 th Mxx_TXER Hold time Mxx_RXER valid after Mxx_GTCLK 1 ns 100 ppm tolerance ÎÎÎÎÎÎ...

Page 64: ... before Mxx_RCLK 2 ns 2 th Mxx_RXD Hold time Mxx_RXD7 Mxx_RXD0 valid after Mxx_RCLK 1 ns 2 th Mxx_RXDV Hold time Mxx_RXDV valid after Mxx_RCLK 1 ns 2 th Mxx_RXER Hold time Mxx_RXER valid after Mxx_RCLK 1 ns ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ Mxx_RXD7 Mxx_RXD0 Mxx_RXDV Mxx_RXER 1 2 Mxx_RCLK Figure 18 GMII Receive Mxx_CRS and Mxx_COL are driven asynchronously by the PHY Mxx_GTCLK is derived directly fr...

Page 65: ... Mxx_GCLK Pulse width low Mxx_RFCLK 2 5 ns 2 th Mxx_GCLK Pulse width high Mxx_RFCLK 2 5 ns 3 tw Mxx_GCLK Cycle time Mxx_RFCLK 8 ns PMA and GMII clock see Figure 20 NO MIN MAX UNIT 1 tr Mxx_GCLK Rise time Mxx_RFCLK 1 ns 2 tf Mxx_GCLK Fall time Mxx_RFCLK 1 ns 3 Accuracy 100 PPM duty cycle 40 60 tr and tf are measured between 20 and 80 VDD 3 3 V min output load GTCLK 20pf Mxx_RFCLK 1 2 3 Figure 20 GM...

Page 66: ...1 NO MIN MAX UNIT 1 tsu Mxx_RXD Setup time Mxx_RXD3 Mxx_RXD0 valid before Mxx_RCLK 8 ns 1 tsu Mxx_RXDV Setup time Mxx_RXDV valid before Mxx_RCLK 8 ns 1 tsu Mxx_RXER Setup time Mxx_RXER valid before Mxx_RCLK 8 ns 2 th Mxx_RXD Hold time Mxx_RXD3 Mxx_RXD0 valid after Mxx_RCLK 8 ns 2 th Mxx_RXDV Hold time Mxx_RXDV valid after Mxx_RCLK 8 ns 2 th Mxx_RXER Hold time Mxx_RXER valid after Mxx_RCLK 8 ns ÎÎÎ...

Page 67: ...TXEN Delay time from Mxx_TCLK to Mxx_TXEN valid 5 15 ns 1 td Mxx_TXER Delay time from Mxx_TCLK to Mxx_TXER valid 5 15 ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Mxx_TXD3 Mxx_TXD0 Mxx_TXEN Mxx_TXER 1 Mxx_TCLK Figure 22 MII Transmit MII clock see Figure 23 NO MIN MAX UNIT 1 tr Mxx_CLK Pulse width low Mxx_RCLK Mxx_TCLK 35 65 2 th Mxx_CLK Pulse width high Mxx_RCLK Mxx_TCLK 35 65 3 tw Mxx_CLK Cycl...

Page 68: ...or high 45 55 tc DX_CLK 4 5 tw TICK Pulse duration tick time 0 5 0 5 tcycle 6 8 tsu DBUS_DATA Setup time DBUS_DATA before tick 0 35 ns 7 9 th DBUS_DATA Hold time DBUS_DATA after tick 0 35 ns 10 11 td DBUS_OUT Delay time DBUS_DATA DBUS_CTRL DBUS_EN from tick 0 635 1 438 tc DX_CLK tcycle Cycle time internal clock 4 tc DX_CLK Not shown in Figure 24 due to scale ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ...

Page 69: ...AD1 SAD0 SDMA valid after SRDY 0 ns 7 th SDATA Hold time SAD7 SAD0 valid after SRDY 0 ns 8 th SCSL Hold time SCS low after SRDY 0 ns 9 td SRDYZH Delay time from SCS to SRDY 10 ns 10 td SRDYHL Delay time from SCS to SRDY 2tc ns 11 td SRDYLH Delay time from SCS to SRDY tc 2tc 10 ns 12 th SCSH Hold time SCS high after SRDY 0 ns 13 tw SRDY Pulse duration SRDY tc ns 14 td SINT Delay time from SRDY to S...

Page 70: ...D Setup time from SRDY to SDATA7 SDATA0 driven 0 ns 8 td SRDYZH Delay time from SCS to SRDY 10 ns 9 td SRDYHL Delay time from SCS to SRDY 0 ns 10 td SDATAZ Delay time from SCS to SDATA7 SDATA0 3 state 0 10 ns 11 td SRDYLH Delay time from SCS to SRDY tc 2tc 10 ns 12 th SCSH Hold time SCS high after SRDY 0 ns 13 tw SRDY Pulse duration SRDY high tc ns When the switch is performing certain internal op...

Page 71: ...n during ECLK high 383 tc 3 th EDIO Data Hold time data after ECLK 0 tc 4 tsu EDIO Data Setup time data before ECLK 383 tc 5 tw ECLK Pulse duration ECLK low during start stop 766 tc 6 tw ECLK Pulse duration ECLK high during start stop 766 tc 7 tw ECLK Data Pulse duration ECLK high during data 383 tc 8 tw ECLK Data Pulse duration ECLK low during data 766 tc 9 fclock ECLK Clock frequency ECLK 98 kHz...

Page 72: ...me LED_CLK 8 tc 2 tw LED_CLK Pulse duration LED_CLK high 4 tc 3 tn LED_CLK Number of LED_CLK pulses in burst 24 4 tc BURST Cycle time LED_CLK burst 4687488 tc 5 tsu LED_DATA Setup time LED_DATA before LED_CLK 4 tc 6 th LED_DATA Hold time LED_DATA after LED_CLK 4 tc During hard reset LED_CLK runs continuously Does not apply during hard reset First LED Second LED Last LED First LED 5 6 2 1 3 4 LED_C...

Page 73: ...nts are plotted on the voltage waveforms IV110 IV110 From Output Under Test Drive Dependent Internal and Input Macro Load Circuit From Output Under Test CL four load values Output Macro Load Circuit tPLH tPHL tPZH tPZL N channel tPZH only P channel tPZL only Figure 30 Loading for Active Transitions High or Low Ion Input tPHZ tPLZ N channel tPLZ only P channel tPHZ only V Figure 31 Loading for High...

Page 74: ... 80 80 20 47 47 tf tr VDD 0 Input 47 tPLH VOH VOL In Phase Output tPHL 47 47 VOH VOL Out of Phase Output tPHL 47 tPHL Figure 33 Internal Push Pull Output Propagation Delay Time Voltage Waveforms 20 80 80 20 47 47 tf tr VDD 0 CMOS Level Input CMOS tPLH VOH VOL LVCMOS TTL Output CMOS tPHL 1 3 V 50 1 3 V 50 TTL tPLH TTL tPHL Figure 34 TTL Output Macro Propagation Delay Time Voltage Waveforms ...

Page 75: ...MEASUREMENT INFORMATION VDD 0 20 47 80 Input active low enable Hi Z Active VOH Hi Z forced low 50 LVCMOS 1 3 V TTL tPZH Output High VOL Hi Z forced high 50 LVCMOS 1 3 V TTL Output Low tPZL VDD 0 20 47 80 Input active low enable Hi Z Active Ion 0 mA tPHZ Output High Ion 0 mA 1 mA Output Low tPLZ 1 mA Figure 35 TTL 3 State Output Disable and Enable Voltage Waveforms ...

Page 76: ...AGE 4073223 A 11 96 A 1 3 2 F E D C K J H G B P N M W V U T R AC AB AA Y AF AE AD L 5 6 4 9 8 7 11 13 12 15 16 14 10 19 18 21 23 22 20 25 26 24 17 Seating Plane SQ 34 80 35 20 0 50 MIN 0 90 0 60 Heat Slug 0 91 NOM 1 70 MAX 31 75 SQ 1 27 0 15 M 0 30 NOTES A All linear dimensions are in millimeters B This drawing is subject to change without notice C Thermally enhanced die down plastic package with ...

Page 77: ...t This component has a RoHS exemption for either 1 lead based flip chip solder bumps used between the die and package or 2 lead based die adhesive used between the die and leadframe The component is otherwise considered Pb Free RoHS compatible as defined above Green RoHS no Sb Br TI defines Green to mean Pb Free RoHS compatible and free of Bromine Br and Antimony Sb based flame retardants Br or Sb...

Page 78: ...ice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertis...

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