Usage Notes and Known Design Exceptions to Functional Specifications
Advisory 1.0.35
UART: Transactions to MDR1 Register May Cause Undesired Effect on UART
Operation
Revisions Affected
2.1, 2.0, 1.0
Details
The UART logic may generate an internal glitch when accessing the MDR1 registers that
causes a dummy under-run condition that will freeze the UART in IrDA transmission. In
UART mode, this may corrupt the transferred data (received or transmitted).
Workarounds
To ensure this problem does not occur, the following software initialization sequence
must be used each time MDR1 must be changed.
1. If needed, set up the UART by writing the required registers, except MDR1.
2. Set the MDR1.MODE_SELECT bit field appropriately.
3. Wait for five L4 clock five UART functional clock cycles.
4. Clear TX and RX FIFO in the FCR register to reset its counter logic.
5. Read RESUME register to resume the halted operation.
Note: Step 5 is for IrDA mode only and can be omitted in UART mode.
Advisory 1.0.36
EMU0 and EMU1: Terminals Must be Pulled High Before ICEPick Samples
Revisions Affected
2.1, 2.0, 1.0
Details
The state of the EMU[1:0] terminals are latched during reset to determine ICEPick boot
mode. For normal device operation, these terminals must be pulled up to a valid high
logic level ( > V
IH
min) before ICEPick samples the state of these terminals, which occurs
[five CLK_M_OSC clock cycles - 10 ns] after the falling edge of WARMRSTn.
Many applications may not require the secondary GPIO function of the EMU[1:0]
terminals. In this case, they would only be connected to pull-up resistors, which ensures
they are always high when ICEPick samples. However, some applications may need to
use these terminals as GPIO where they could be driven low before reset is asserted.
This usage of the EMU[1:0] terminals may require special attention to ensure the
terminals are allowed to return to a valid high-logic level before ICEPick samples the
state of these terminals.
When any device reset is asserted, the pin mux mode of EMU[1:0] terminals configured
to operate as GPIO (mode 7) will change back to EMU input (mode 0) on the falling
edge of WARMRSTn. This only provides a short period of time for the terminals to return
high if driven low before reset is asserted.
Workarounds
If the secondary GPIO function of the EMU[1:0] terminals is not required, only connect
these terminals to pull-up resistors.
If the EMU[1:0] terminals are configured to operate as GPIO, the product should be
designed such these terminals can be pulled to a valid high-logic level within 190 ns
after the falling edge of WARMRSTn.
37
SPRZ360F – October 2011 – Revised November 2013
Sitara™ AM335x ARM
®
Cortex™-A8 Microprocessors (MPUs) (Silicon
Revision 2.1, 2.0, 1.0)
Copyright © 2011–2013, Texas Instruments Incorporated
