Usage Notes and Known Design Exceptions to Functional Specifications
Advisory 1.0.32
TSC_ADC: Terminals May be Temporarily Connected Together Through Internal
Paths During Power-up Sequence
Revisions Affected
2.1, 2.0, 1.0
Details
Any one or more of the TSC_ADC terminals (AIN[7:0], VDDA_ADC, VREFP,
VSSA_ADC, and VREFN) may be temporarily connected together through internal paths
during the power-up sequence. These internal connections can occur when the
VDDA_ADC power source is applied while the VDD_CORE supply is not applied.
The temporary internal connections may occur in any or all of the four analog
multiplexers in the TSC_ADC analog front end (AFE). This occurs because the
VDD_CORE supply is used to power the decoder logic that selects which analog switch
is enabled in each analog multiplexer. It is possible for multiple analog switches in each
multiplexer to be enabled while the decoder logic does not have a valid power source.
When this occurs, all multiplexer inputs that have their analog switch enabled will
simultaneously be connected to the multiplexer output which causes the multiplexer
output and all enabled inputs to be connected together.
To better understand all of the possible internal connection paths, read the following
paragraphs while referencing the Analog Front End (AFE) Functional Block Diagram,
which can be found in the Touchscreen Controller chapter of the
AM335x ARM®
Cortex™-A8 Microprocessors (MPUs) Technical Reference Manual
(
The VDDA_ADC, AN0, AN2, and VREFP terminals are connected to four of the five
INT_VREFP (5:1 multiplexer) inputs which allow either one or both power sources
(VDDA_ADC and VREFP) to be connected to the AIN0 terminal, AIN2 terminal, and two
inputs of each 9:1 multiplexer.
The VSSA_ADC, AIN1, AIN3, and VREFN terminals are connected to the four VREFM
(4:1 multiplexer) inputs which allows one or both ground references (VSSA_ADC and
VREFN) to be connected to the AIN1 terminal, AIN3 terminal, and two inputs of each 9:1
multiplexer.
The AIN[7:0] and VREFN terminals are connected to the nine INP (9:1 multiplexer) and
INM (9:1 multiplexer) inputs which allow any or all AIN[7:0] and VREFN terminals to be
connected together.
Workarounds
•
TSC_ADC AIN terminals used with a resistive touchscreen:
No action required for these AIN terminals.
•
TSC_ADC AIN terminals used as ADC inputs:
Insert a series resistor on each of these AIN terminals to limit the output current to an
acceptable level for the attached device during this temporary period when
VDD_CORE is not applied during power-up. For example: If the attached device has
a minimum output impedance (Rsource_min) of 20
Ω
and can drive its output as low
as VSSA_ADC (0 V) with a maximum output current of 1 mA and the respective AIN
terminal is temporarily connected to VDDA_ADC (1.89-V maximum supply voltage),
the minimum series resistance (Rseries_min) would need to be 1890
Ω
minus
Rsource_min to limit the current to 1 mA. Therefore, a series resistor greater than
1870
Ω
should be inserted on the analog input signal to protect the attached device.
The effect on ADC performance also needs to be considered when inserting a series
resistor to limit current. Additional series resistance will increase the time required for
the source to charge the ADC input capacitor. The ADC accuracy will be reduced if
the input capacitor is not completely charged during the sampling time. The following
formula should be used to calculate the maximum resistance of the series resistor.
Rseries_max = [(ADC_ 1) *( Sampl 2) / (116 x 10
-12
) * (CLK_M_OSC)] -
200
Ω
- Rsource_max
34
SPRZ360F – October 2011 – Revised November 2013
Sitara™ AM335x ARM
®
Cortex™-A8 Microprocessors (MPUs) (Silicon
Revision 2.1, 2.0, 1.0)
Copyright © 2011–2013, Texas Instruments Incorporated
