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Usage Notes and Known Design Exceptions to Functional Specifications

Advisory 1.0.13

USB: Data May be Lost When USB Subsystem is Operating in DMA Mode and
More Than One Endpoint is Transferring Data

Revisions Affected

1.0

Details

Data loss may occur due to a USB data toggle synchronization error that occurs when
an internal data toggle counter is erroneously reset from the DATA1 state to the DATA0
state while the USB subsystem is actively receiving data from more than one endpoint.
The erroneous reset of the data toggle counter occurs because the associated logic in
the USB subsystem DMA contains an error that does not support the correct data toggle
update with data transfers from multiple endpoints.

If the DATA1 state is erroneously reset to the DATA0 state immediately following a USB
transaction in which the PID is DATA0, the transmitter and receiver become de-
synchronized. This data toggle synchronization error causes the receiver, per the USB
specification, to silently discard the non-synchronized packet, which causes the packet
and any data contain therein to be lost.

NOTE:

For more information related to the definition of DATA0 and DATA1 PIDs

and functional requirements of data toggle synchronization, see sections
8.4.4 and 8.6 of the

Universal Serial Bus Specification Revision 2.0

.

Workarounds

•

Operating in USB host mode - The workaround involves detecting and correcting the
data toggle mismatch by software after receiving each USB packet. In order to
implement this workaround, the CPPI4.1 DMA must be configured to operate in
transparent mode; generic RNDIS mode cannot be used. Software must save the
previous data toggle value then compare the current data toggle value and the saved
value to detect a data toggle mismatch. If a synchronization error is detected, it must
be corrected by simultaneously writing 1b to the data toggle write enable and data
toggle bits in the respective RxCSR registers.

•

Operating in USB device mode - There is no workaround for this mode of operation.

19

SPRZ360F – October 2011 – Revised November 2013

Sitara™ AM335x ARM

®

Cortex™-A8 Microprocessors (MPUs) (Silicon

Revision 2.1, 2.0, 1.0)

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Copyright © 2011–2013, Texas Instruments Incorporated

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Summary of Contents for Sitara AM1335 Series

Page 1: ...Sitara AM335x ARM Cortex A8 Microprocessors MPUs Silicon Revisions 2 1 2 0 1 0 Silicon Errata Literature Number SPRZ360F October 2011 Revised November 2013 ...

Page 2: ...t USB Boot ROM Code Uses Default DATAPOLARITY 9 3 1 4 Boot Multiplexed Signals GPMC_WAIT0 GMII2_CRS and RMII2_CRS_DV Cause NAND Boot Issue 9 3 1 5 Pin Multiplexing Valid IO Sets and Restrictions 10 3 1 6 Boot Multiplexed Signals GPMC_WAIT0 and GMII2_CRS Cause NAND Boot Issue 10 3 1 7 OSC1 RTC_XTALIN Terminal Has an Internal Pull up Resistor When OSC1 is Disabled 11 3 2 Known Design Exceptions to F...

Page 3: ... Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical specifications null Production version of the silicon die that is fully qualified Support tool development evolutionary flow TMDX Development support product that has not yet completed Texas Instruments internal qualification testing TMDS Fully qualified development support product X and P...

Page 4: ...evices have a blank at the beginning of the device name B The AM3352 and AM3359 devices shown in this device marking example are two of several valid part numbers for the AM335x family of devices C The device revision code is the device revision A B and so on D YM denotes year and month E LLLL denotes Lot Trace Code F 962 is a generic family marking ID G G1 denotes green lead free H ZCE or ZCZ is ...

Page 5: ...gister located at address 0x44E10600 provides a 4 bit binary value that represents the device revision The ROM code revision can be read from address 2BFFCh The ROM code version consists of two decimal numbers major and minor The major number is always 22 minor number counts ROM code version The ROM code version is coded as hexadecimal readable values for example ROM version 22 02 is coded as 0000...

Page 6: ...ly Debug Subsystem EMU 4 2 Signals Are Not Available by Advisory 1 0 2 X X X Default After Reset Debug Subsystem Internal Inputs Tied off to the Wrong Advisory 1 0 3 X X X Value Advisory 1 0 4 PRU ICSS Clock Domain Crossing CDC Issue X Advisory 1 0 5 RTC 32 768 kHZ Clock is Gating Off X EXTINTn Input Function of the EXTINTn Terminal is Advisory 1 0 6 X Inverted Advisory 1 0 7 Boot Ethernet Boot RO...

Page 7: ...mporarily Stalls if an Attempt to Boot Advisory 1 0 25 X X X from Ethernet is Not Successful Advisory 1 0 26 I2C SDA and SCL Open Drain Output Buffer Issue X X Advisory 1 0 27 LCDC LIDD DMA Mode Issue X X X LCDC Raster Mode Hardware Auto Underflow Restart Advisory 1 0 28 X X X Does Not Work Latch up Performance Latch up Performance Limits for Advisory 1 0 29 X X Silicon Revsions 1 0 and 2 0 OSC0 a...

Page 8: ...the LCD Controller with this connection scheme limits the use of RGB565 mode Any data generated for the RGB565 mode requires the red and blue color data values be swapped in order to display the correct color Figure 2 RGB888 Mode LCD Controller Output Pin Mapping LCD_DATA 23 0 When operating the LCD Controller in RGB565 mode the LCD panel should be connected as shown in Figure 3 Using the LCD Cont...

Page 9: ...The GMII2_CRS or RMII2_CRS_DV signal is required by the respective MII or RMII Ethernet PHY and the only pin multiplexing option for these signals is GPMC_WAIT0 In this case there are two sources that need to be connected to the GPMC_WAIT0 terminal The NAND READY or BUSY output must source the GPMC_WAIT0 terminal during NAND boot and the MII CRS or RMII CRS_DV output must source the GPMC_WAIT0 ter...

Page 10: ... terminal This causes a problem when the system must support NAND boot while an MII Ethernet PHY is connected to port 2 of the Ethernet media access controller and switch CPSW The GPMC_WAIT0 signal is required for NAND boot The GMII2_CRS signal is required by the MII Ethernet PHY and the only pin multiplexing option for these signals is GPMC_WAIT0 In this case there are two sources that need to be...

Page 11: ...nded an external pull down resistor to be connected to the RTC_XTALIN terminal if OSC1 was not used The recommendation should have been to leave this terminal open circuit when not using OSC1 Connecting an external pull down to the RTC_XTALIN terminal may cause unexpected leakage current The current recommendation is to remove any external pull down resistor from the RTC_XTALIN terminal and leave ...

Page 12: ... export of debug trace messages on the EMU 4 0 signals The AM335x EMU 4 2 signals can not be used to export trace messages from the Debug subsystem since AM335x does support warm reset and the EMU 4 2 signals are not assigned to pins after reset is asserted Workarounds Do not assert warm reset while performing trace functions Advisory 1 0 3 Debug Subsystem Internal Inputs Tied off to the Wrong Val...

Page 13: ...terminal is held low This issue has the following side effects The RTC counters stop incrementing when the 32 768 kHz clock is gated This causes the RTC to lose time while the clock is gated A wakeup event applied to the EXT_WAKEUP input terminal is masked if the EXT_WAKEUP_DB_EN bit in the RTC PMIC register 0x98 is set to 1 which enables the de bounce function for the EXT_WAKEUP input This occurs...

Page 14: ...e specification Workarounds When using Ethernet boot an external PHY that updates the Register 0 link speed selection bits 0 6 and 0 13 to reflect the current operating speed is required Advisory 1 0 8 Boot Ethernet Boot ROM Code Sends an Incorrect Vendor Class Identifier in BOOTP Packet Revisions Affected 1 0 Details When using Ethernet boot the device ROM code should send a BOOTP request with a ...

Page 15: ...RM Cortex A8 TINT6 interrupt 94 TIMER6 Capture Event Event Capture Mux event 9 EMAC and Switch C0_TX_PEND Configuration The following configurations are required to use timer capture module interrupts TIMER5 and TIMER6 are enabled with capture mode during initialization Set bit 2 of the TIMER5 IRQENABLE set register located at 0x4804_602C to 1b Set bit 2 of the TIMER6 IRQENABLE set register locate...

Page 16: ...learing the C0_xx_EN field in the respective C0_RX_EN C0_TX_EN register Acknowledge the interrupt by writing the appropriate RX or TX vector to the CPDMA_EOI_VECTOR register Process all received or transmitted packets Enable the desired CPSW interrupts in the C0_xx_EN field in the respective C0_RX_EN C0_TX_EN register 16 SPRZ360F October 2011 Revised November 2013 Sitara AM335x ARM Cortex A8 Micro...

Page 17: ...be enabled to insert delays required to meet the setup and hold timing requirements of the AM335x device and attached RGMII PHY A timing analysis is recommended before the printed circuit board PCB design has been completed in case it is necessary to insert additional delays on the RGMII signals connecting the AM335x device and attached RGMII PHY It is necessary to insert PCB delays if the RGMII P...

Page 18: ...and mismatched terminations on the differential signal pair may cause reflections to propagate longer than expected which allows the transceiver to detect these reflections of its own transmit data as receive data Workarounds There is no workaround for this issue To prevent an unexpected response to any invalid short packets attach only USB devices that are compliant with the USB specification To ...

Page 19: ...non synchronized packet which causes the packet and any data contain therein to be lost NOTE For more information related to the definition of DATA0 and DATA1 PIDs and functional requirements of data toggle synchronization see sections 8 4 4 and 8 6 of the Universal Serial Bus Specification Revision 2 0 Workarounds Operating in USB host mode The workaround involves detecting and correcting the dat...

Page 20: ...CONF_GPMC_A7 0x44E1_085C CONF_GPMC_A8 0x44E1_0860 CONF_GPMC_A9 0x44E1_0864 CONF_GPMC_A10 0x44E1_0868 CONF_GPMC_A11 0x44E1_086C CONF_GPMC_WAIT0 0x44E1_0870 CONF_GPMC_WPN 0x44E1_0874 CONF_GPMC_BEN1 0x44E1_0878 CONF_MII1_COL 0x44E1_0908 CONF_MII1_CRS 0x44E1_090C CONF_MII1_RX_ER 0x44E1_0910 CONF_MII1_TX_EN 0x44E1_0914 CONF_MII1_RX_DV 0x44E1_0918 CONF_MII1_TXD3 0x44E1_091C CONF_MII1_TXD2 0x44E1_0920 CO...

Page 21: ...MPU PLL CLK_M_OSC N REFCLK M M2 CLKOUT MHz CM_CLKSEL_DPLL_MPU 6 0 MHz CM_CLKSEL_DPLL_MPU 18 8 CM_DIV_M2_DPLL_MPU 4 0 MHz 19 2 95 0 2 1375 1 275 24 23 1 275 1 275 25 24 1 275 1 275 26 25 1 275 1 275 Advisory 1 0 16 RMII 50 MHz RMII Reference Clock Output Does Not Satisfy Clock Input Requirements of RMII Ethernet PHYs Revisions Affected 2 1 2 0 1 0 Details The 50 MHz RMII reference clock output is s...

Page 22: ...nternal pull downs are configured by writing 0011_1111_1111_0000_0000_00pp_pppp_pppp where p previous binary value to the DDR_DATA0_IOCTRL and DDR_DATA1_IOCTRL registers Advisory 1 0 18 ROM Ethernet Boot Code Does Not Change Default Direction of RMII1 Reference Clock When Booting from Ethernet Using RMII Revisions Affected 1 0 Details The default direction of the RMII1 reference clock is output mo...

Page 23: ... compensate READ and WRITE timing 1 Disable automated hardware READ and WRITE leveling by setting the REG_RDWRLVL_EN bit in the RDWR_LVL_RMP_CTRL register to 0b 2 Configure all EMIF4D registers including AC timing values as required for the attached DDR3 memory device 3 Determine the initial seed DLL ratio values to be used in the software leveling algorithm These values are based on board trace l...

Page 24: ... domain of the ZCZ package when configured for OPP100 because SmartReflex may reduce the VDD_MPU voltage to OPP50 levels Advisory 1 0 15 describes why operating the ARM Cortex A8 at the lower voltage defined by OPP50 is not supported For more details related to this issue see Advisory 1 0 15 SmartReflex is not supported on the ZCE package SmartReflex is supported on the ZCZ package for the followi...

Page 25: ...1 0 23 Ethernet Media Access Controller and Switch Subsystem Reset Isolation Feature is Not Supported Revisions Affected 2 1 2 0 1 0 Details The Ethernet Media Access Controller and Switch CPSW subsystem may lock up if the Reset Isolation feature is enabled when a warm reset is applied while the host port is transmitting data Since most warm reset sources can be asynchronous events this lock up co...

Page 26: ...VDD_MPU and VDD_CORE power supplies to OPP100 defined voltages before any of these resets sources are asserted Workarounds Only source the PWRONRSTn terminal from a power management circuit that always returns VDD_MPU and VDD_CORE power supplies to OPP100 defined voltages before asserting PWRONRSTn There are two possible workarounds that can be applied to the other two reset sources The first work...

Page 27: ...the purpose of updating MMC0 boot code However this boot sequence attempts to boot from Ethernet first which would insert an undesirable long delay when booting from MMC0 Workarounds There is no device level workaround but it may be possible to develop a system level solution that mitigates the effect of this issue when an occasional Ethernet boot is required In the example described above the sys...

Page 28: ...uration of the unexpected high level pulse when the slave begins its ACK cycle This occurs because the slave may already be driving SDA low before the unexpected high level pulse occurs The glitch that occurs on SDA as a result of this short period of contention does not cause any I2C protocol issue but the peak current applies unwanted stress to both I2C devices and potentially increases power su...

Page 29: ... all attached I2C devices while the other option supports a maximum high level input current of 100 uA to all attached I2C devices Table 6 Recommended Values for Series Termination Resistor and Pullup Resistor I2C SIGNAL LEVEL AND SERIES TERMINATION RESPECTIVE VDDSHVx PULLUP RESISTOR Ω NOTES RESISTOR Ω POWER SUPPLY V Maximum high level input 1 8 60 1500 current up to 200 µA Maximum high level inpu...

Page 30: ...roper FIFO operation This workaround has a side effect that needs to be considered The LCDC drives the LCD control signals to their active state when software reset is asserted if the active states of the LCD panel inputs are opposite the LCDC default states If this is the case it may be necessary to add a hardware isolation circuit to the LCD panel chip select signal that disconnects the LCDC out...

Page 31: ...bits in the CLKC_RESET register 4 Wait several clock cycles 5 Write 0 to the MAIN_RST or DMA_RST and CORE_RST bits in the CLKC_RESET register 6 Write 1 to the LCDEN bit in the RASTER_CTRL register Advisory 1 0 29 Latch up Performance Latch up Performance Limits for Silicon Revsions 1 0 and 2 0 Revisions Affected 2 0 1 0 Details Latch up performance was improved in silicon revision 2 1 devices and ...

Page 32: ...y produce clock glitches to various internal logic circuits These clock glitches may cause unexpected behavior Workarounds Connect the VSS_OSC and VSS_RTC terminals and respective crystal circuit component grounds directly to the nearest PCB digital ground making it more difficult for noise to couple into the crystal circuit Advisory 1 0 31 TSC_ADC False Pen up Interrupts Revisions Affected 2 1 2 ...

Page 33: ...screen capacitance as shown in Figure 6 Figure 6 Pen down Remains Active in Idle Step Another method is available for 4 wire touchscreen implementations It this case it is possible to enable and configure one of the 16 steps to emulate the Charge step with the strong pull up turned on as the step before the actual Charge step that has been configured like the Idle step with the strong pull up turn...

Page 34: ...inals are connected to the four VREFM 4 1 multiplexer inputs which allows one or both ground references VSSA_ADC and VREFN to be connected to the AIN1 terminal AIN3 terminal and two inputs of each 9 1 multiplexer The AIN 7 0 and VREFN terminals are connected to the nine INP 9 1 multiplexer and INM 9 1 multiplexer inputs which allow any or all AIN 7 0 and VREFN terminals to be connected together Wo...

Page 35: ...ted VSSA_ADC No action required for the VREFP and VREFN terminals TSC_ADC VREFP terminal not connected to VDDA_ADC and VREFN terminal not connected to VSSA_ADC Insert a series resistor on each VREFP and VREFN terminal with a 0 1 uF decoupling capacitor connected directly to each VREFP and VREFN terminal The series resistor value should be selected to limit output current to an acceptable level for...

Page 36: ...None Advisory 1 0 34 USB2PHY Register Accesses After a USB Subsystem Soft Reset May Lock Up the Entire System Revisions Affected 2 1 2 0 1 0 Details The synchronization bridge connecting the USB2PHY register interface to the L3S interconnect may hang and lock up the entire system When there is a sequence of any USB2PHY register access followed by a USB subsystem soft reset initiated with the SOFT_...

Page 37: ...in before ICEPick samples the state of these terminals which occurs five CLK_M_OSC clock cycles 10 ns after the falling edge of WARMRSTn Many applications may not require the secondary GPIO function of the EMU 1 0 terminals In this case they would only be connected to pull up resistors which ensures they are always high when ICEPick samples However some applications may need to use these terminals...

Page 38: ...ing Power up Sequence 34 Added Advisory 1 0 33 USB Host USB Low Speed Receive to Transmit Inter Packet Delay 36 Added Advisory 1 0 34 USB2PHY Register Accesses After a USB Subsystem Soft Reset May Lock Up the Entire System 36 Added Advisory 1 0 35 UART Transactions to MDR1 Register May Cause Undesired Effect on UART Operation 37 Added Advisory 1 0 36 EMU0 and EMU1 Terminals Must Be Pulled High Bef...

Page 39: ...esponsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failur...

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