Usage Notes and Known Design Exceptions to Functional Specifications
Advisory 1.0.4
PRU-ICSS: Clock Domain Crossing (CDC) Issue
Revisions Affected
1.0
Details
The PRU-ICSS has a clock domain crossing issue when the MII receive multiplexer is
configured to connect PR1_MII1 signals to PRU0 and PR1_MII0 signals to PRU1.
The multiplexer logic always uses the PR1_MII_MR0_CLK input to synchronize the
PRU0 MII receive signals and the PR1_MII_MR1_CLK input to synchronize the PRU1
MII receive signals. This cause the wrong clock to be used when the MII receive
multiplexer is configured to connect PR1_MII1 signals to PRU0 and PR1_MII0 signals to
PRU1.
As a result of this issue, support for EtherCAT media redundancy is not available.
Workarounds
There is no workaround for this issue.
Advisory 1.0.5
RTC: 32.768-kHZ Clock is Gating Off
Revisions Affected
1.0
Details
The RTC has a clock gating issue that stops the internal 32.768-kHz clock when the
VDD_CORE voltage domain drops below the recommended operating range or the
PWRONRSTn input terminal is held low. This issue has the following side effects:
•
The RTC counters stop incrementing when the 32.768-kHz clock is gated. This
causes the RTC to lose time while the clock is gated.
•
A wakeup event applied to the EXT_WAKEUP input terminal is masked if the
EXT_WAKEUP_DB_EN bit in the RTC PMIC register (0x98) is set to 1 which enables
the de-bounce function for the EXT_WAKEUP input. This occurs because the
32.768-kHz clock is being used to clock the de-bounce circuit.
Workarounds
Do not turn off the VDD_CORE power source or source a logic low to the PWRONRSTn
input while expecting RTC to keep an accurate time.
Do not enable the de-bounce circuit on the EXT_WAKEUP input if an external wakeup
event needs to be detected while the 32.768-kHz clock is gated.
Advisory 1.0.6
EXTINTn: Input Function of the EXTINTn Terminal is Inverted
Revisions Affected
1.0
Details
The EXTINTn input is active high.
Workarounds
Use an active high interrupt source or use an external inverter to change the polarity of
any active low interrupt source.
13
SPRZ360F – October 2011 – Revised November 2013
Sitara™ AM335x ARM
®
Cortex™-A8 Microprocessors (MPUs) (Silicon
Revision 2.1, 2.0, 1.0)
Copyright © 2011–2013, Texas Instruments Incorporated
