Exception Model
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SLAU356I – March 2015 – Revised June 2019
Copyright © 2015–2019, Texas Instruments Incorporated
Cortex-M4F Processor
1.5.1 Exception States
Each exception is in one of the following states:
•
Inactive: The exception is not active and not pending.
•
Pending: The exception is waiting to be serviced by the processor. An interrupt request from a
peripheral or from software can change the state of the corresponding interrupt to pending.
•
Active: An exception that is being serviced by the processor but has not completed.
NOTE:
An exception handler can interrupt the execution of another exception handler. In this case,
both exceptions are in the active state.
•
Active and Pending: The exception is being serviced by the processor, and there is a pending
exception from the same source.
1.5.2 Exception Types
The exception types are:
•
Reset: Reset is invoked on power up or a warm reset. The exception model treats reset as a special
form of exception. When reset is asserted, the operation of the processor stops, potentially at any point
in an instruction. When reset is deasserted, execution restarts from the address provided by the reset
entry in the vector table. Execution restarts as privileged execution in Thread mode.
•
NMI: A nonmaskable Interrupt (NMI) can be signaled using the NMI signal or triggered by software
using the Interrupt Control State register (ICSR). This exception has the highest priority other than
reset. NMI is permanently enabled and has a fixed priority of -2. NMIs cannot be masked or prevented
from activation by any other exception or preempted by any exception other than reset.
•
Hard Fault: A hard fault is an exception that occurs because of an error during exception processing,
or because an exception cannot be managed by any other exception mechanism. Hard faults have a
fixed priority of -1, meaning they have higher priority than any exception with configurable priority.
•
Memory Management Fault: A memory management fault is an exception that occurs because of a
memory protection related fault, including access violation and no match. The MPU or the fixed
memory protection constraints determine this fault, for both instruction and data memory transactions.
This fault is used to abort instruction accesses to Execute Never (XN) memory regions, even if the
MPU is disabled.
•
Bus Fault: A bus fault can occur under various conditions as listed below
–
Accessing a vacant address in the memory map
–
Accessing 16-bit peripherals with 32-bit accesses
–
Any other condition now allowed by the system e.g. write access to ROM memory
•
Usage Fault. A usage fault is an exception that occurs because of a fault related to instruction
execution, such as:
–
An undefined instruction
–
An illegal unaligned access
–
Invalid state on instruction execution
–
An error on exception return
An unaligned address on a word or halfword memory access or division by zero can cause a usage
fault when the core is properly configured.
•
SVCall: A supervisor call (SVC) is an exception that is triggered by the SVC instruction. In an OS
environment, applications can use SVC instructions to access OS kernel functions and device drivers.
•
Debug Monitor: This exception is caused by the debug monitor (when not halting). This exception is
only active when enabled. This exception does not activate if it is a lower priority than the current
activation.
•
PendSV: PendSV is a pendable, interrupt-driven request for system-level service. In an OS
environment, use PendSV for context switching when no other exception is active. PendSV is triggered
using the Interrupt Control State register (ICSR).
•
SysTick: A SysTick exception is an exception that the system timer generates when it reaches zero
