RAM Grouping and Algorithm
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SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Programmable Built-In Self-Test (PBIST) Module
7.1.3.1
On-chip ROM
The on-chip ROM contains the information regarding the algorithms and memories to be tested.
7.1.3.2
Host Processor Interface to the PBIST Controller Registers
The Cortex-R4F CPU can select the algorithm and RAM groups for the memories' self-test from the on-
chip ROM based on the application requirements. Once the self-test has executed, the CPU can query the
PBIST controller registers to identify any memories that failed the self-test and to then take appropriate
next steps as required by the application's author.
7.1.3.3
Memory Data Path
This is the read and write data path logic between different system and peripheral memories tightly
coupled to the PBIST memory interface. The PBIST controller executes each selected algorithm on each
valid memory group sequentially until all the algorithms are executed.
NOTE:
Not all algorithms are designed to run on all RAM groups. If an algorithm is selected to run
on an incompatible memory, this will result in a failure. Refer to
and for RAM
grouping and algorithm information.
7.2
RAM Grouping and Algorithm
gives the list of RAM groups and their types supported on the device. maps the different
algorithms supported in application mode for the RAM groups with the background patterns used for the
particular algorithm.
NOTE:
March13 is the most recommended algorithm for the memory self-test.
