Safety Features
309
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Tightly-Coupled RAM (TCRAM) Module
6.3.2 Support for Cortex-R4F CPU's Address and Control Bus Parity Checking
The Cortex-R4F CPU calculates a single parity-bit for the TCRAM address and control signals. The
TCRAM interface module also computes this parity bit based on the CPU's address bus and control
signals. The computed parity bit is compared against the parity bit received from the CPU. A mismatch is
signaled as an Address Parity Failure to the Error Signaling Module (ESM) group2 channel 10 or 12.
There is a separate address parity failure error channel for B0TCM and B1TCM.
The 64-bit TCRAM address which fails the parity check is captured in the
register as an
offset from the base address of the TCRAM (0x08000000 by default). The TCRAM interface module also
indicates the type of access, read or write, that failed the parity check. This is indicated by the
RADDR_PAR_FAIL or the WADDR_PAR_FAIL status flags in the
register.
The RAMERRSTATUS and RAMPERRADDR registers must be cleared by the application in order for the
TCRAM interface module to continue capturing subsequent errors and error addresses.
The parity scheme used for the described parity checking mechanism is defined by the global system
parity selection. This can be configured using the DEVPARSEL field of the DEVCR1 control register in the
system module. This device-wide parity scheme can be overridden inside the TCRAM interface module by
configuring the Address Parity Override field in the
register.
NOTE:
No Change Of Parity Scheme On-The-Fly:
The TCRAM interface module does not support
on-the-fly change to the parity scheme being used for checking the CPU address bus and
control bus. The application must ensure that the parity polarity (odd or even) is not changed
while there is an ongoing access to the TCRAM.
6.3.3 Redundant Address Decode
The TCRAM interface module generates the memory selects for each of the TCRAM banks as well as the
ECC memory based on the CPU address. The logic to generate these memory selects is duplicated and
the outputs compared to detect any address decode errors. A mismatch is indciated as an Address Error
to the Error Signaling Module (ESM), one signal for B0TCM and one for B1TCM. The TCRAM or ECC
address that caused the fault is captured in the
register. This 64-bit-aligned address is
stored as an offset from the base of the TCRAM or ECC memory.
As described earlier, each individual physical RAM bank is 36 bits wide. Each RAM bank contributes 32
bits of data and 4 bits of ECC when the bus master performs a 64-bit read from the TCRAM. Each
TCRAM bank receives a memory select and the address from the TCRAM interface module. Any
difference between the address and the memory selects results in wrong data and ECC pair being sent to
the CPU. The CPU's SECDED block will detect this data error.
The TCRAM interface module also supports a mechanism to test the operation of the redundant address
decode logic and the compare logic. This testing is supported by providing a test stimulus, and can be
triggered by the application by configuring the
register. The address of any error identified
during testing of the redundant address decode and compare logic is not captured in the
RAMUERRADDR register.
NOTE:
Address decode checking when in compare logic test mode:
When the address decode
and compare logic test mode is enabled, the redundant address decode and compare logic
is not available for checking the proper generation of the memory selects for the TCRAM and
ECC memory.
6.4
TCRAM Auto-Initialization
The RAM memory can be initialized by using the dedicated auto-initialization hardware. The TCRAM
Module initializes the entire memory when the auto-initialization is enabled by the INIT_DOMAIN register
upon receiving a MMI_INIT pulse from the system module. All enabled RAM data memory locations are
initialized to zeros and the ECC memory is initialized to the correct ECC value for zeros, that is, 0Ch.
