Module Operation
1708
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
RAM Trace Port (RTP)
Table 31-2. Encoding of Status Bits in Trace Mode Packet Format
STAT[1:0]
Status
0
normal entry CPU
1h
normal entry other Master
2h
reserved
3h
overflow of the dedicated FIFO
In the event of a FIFO overflow, an overflow will be signaled in the status bits of the next transmitted
packet of that particular FIFO. The last entry in the FIFO will not be overwritten by the new data.
Table 31-3. Encoding of SIZE bits in Trace Mode Packet Format
SIZE[1:0]
Write/Read Size
0
8 bit
1h
16 bit
2h
32 bit
3h
64 bit
Table 31-4. Encoding of REG in Trace Mode Packet Format
REG
Region
0
1
1
2
The packet will be split up into several subpackets when transmitted over the RTP port pins depending on
the port width configured. The port width is configured with bits PW[1:0] in the RTPGLBCTRL register
(
). For certain port width configurations and write/read sizes, the number of bits in a packet
does not exactly match the port width for the last subpacket. The remaining bits will be filled with zeros.
Table 31-5. Number of Transfers/Packet
Write/Read Size in bits
Port Width
8
16
32
64
2
16 --> 16
20 --> 20
28 --> 28
44 --> 44
4
8 --> 8
10 --> 10
14 --> 14
22 --> 22
8
4 --> 4
5 --> 5
7 --> 7
11 --> 11
16
2 --> 2
2.5 --> 3
3.5 --> 4
5.5 --> 6
Example: For a 16-bit port and with data of 16-bit, the last transfer has to be padded with eight 0s. This
effectively results in a transfer of 48 bits instead of 40. However the whole transfer is completed in 3
RTPCLK cycles.
For a detailed description of the representation of the packet on the RTP port pins, please refer to
.
