Control Registers
1183
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin
Option (MibSPIP)
NOTE:
In multi-buffer mode, INTVECT0 contains the interrupt for the highest priority transfer group.
A read from INTVECT0 automatically causes the next-highest priority transfer group's
interrupt status to get loaded into INTVECT0 and its corresponding SUSPEND flag to get
loaded into SUSPEND0. The transfer group with the lowest number has the highest priority,
and the transfer group with the highest number has the lowest priority.
Reading the INTVECT0 register when the RXOVRN interrupt is indicated in multi-buffer
mode does not clear the RXOVRN flag and hence does not clear the vector. The RXOVRN
interrupt vector may be cleared in multi-buffer mode either by write-clearing the RXOVRN
flag in the SPI Flag Register (SPIFLG) or by reading the RXRAM Overrun Buffer Address
Register (RXOVRN_BUF_ADDR).
24.9.23 Interrupt Vector 1 (INTVECT1)
NOTE:
The TG interrupt is not available in SPI in compatibility mode compatibility mode. Therefore,
there is no possibility to access this register in compatibility mode.
Figure 24-52. Interrupt Vector 1 (INTVECT1) [offset = 64h]
31
16
Reserved
R-0
15
6
5
1
0
Reserved
INTVECT1
SUSPEND1
R-0
R-0
R-0
LEGEND: R = Read only; -
n
= value after reset
Table 24-31. Transfer Group Interrupt Vector 1 (INTVECT1)
Bit
Field
Value
Description
31-6
Reserved
0
Reads return 0. Writes have no effect.
5-1
INTVECT1
INTVECT1. Interrupt vector for interrupt line INT1.
Returns the vector of the pending interrupt at interrupt line INT1. If more than one interrupt is
pending, INTVECT1 always references the highest prior interrupt source first.
Note: This field reflects the status of the SPIFLG register in vector format. Any updates to
the SPIFLG register will automatically cause updates to this field.
0
There is no pending interrupt.
SPI mode only.
11h
Error Interrupt pending. The lower half of SPIINT1 contains more details about the type of error.
SPI mode only.
13h
The pending interrupt is a Receive Buffer Overrun interrupt.
SPI mode only.
12h
The pending interrupt is a Receive Buffer Full interrupt.
SPI mode only.
14h
The pending interrupt is a Transmit Buffer Empty interrupt.
SPI mode only.
All Other
Combinations
Reserved. These bit combinations should not occur.
SPI mode only.
0
SUSPEND1
Transfer suspended / Transfer finished interrupt flag.
Every time INTVECT1 is read by the host, the corresponding interrupt flag of the referenced
transfer group is cleared and INTVECT1 is updated with the vector coming next in the priority
chain.
0
The interrupt type is a transfer finished interrupt. In other words, the buffer array referenced by
INTVECT1 has asserted an interrupt because all of data from the transfer group has been
transferred.
1
The interrupt type is a transfer suspended interrupt. In other words, the transfer group referenced
by INTVECT1 has asserted an interrupt because the buffer to be transferred next is in suspend-to-
wait mode.
