Hardware References
7
SPRUIC4A – January 2017 – Revised December 2017
Copyright © 2017, Texas Instruments Incorporated
Piccolo F280049C controlCARD Information Guide
Table 2. Hardware References
Connectors
J1:A
Emulation/UART connector - USB mini A connector used to provide xds100v2 emulation and
USB-to-UART(SCI) communication through FTDI logic. S1:A determines which connections are
enabled to the MCU.
Jumpers
J1
FSI Connector - Gives an ability to connect FSI signals from the F28004x to another board.
LEDs
D1
Controlled by GPIO-31 with negative logic (red)
D2
Controlled by GPIO-34 with negative logic (red)
D3
Turns on when the controlCARD is powered ON (green)
D2:A
Turns on when ISO JTAG logic is powered on (green)
D3:A
JTAG/UART RX toggle indicator (blue)
D4:A
JTAG/UART TX toggle indicator (blue)
Resistors and Capacitors (default setting in BOLD)
R18, R19, R21, R22
GPIO22/23 configuration resistors
These resistors allow the user to choose whether GPIO22/23 is used as GPIO (and go to the
baseboard) or whether they will be used in conjunction with the F28004x MCU’s internal DC/DC
capability:
•
R18,R19 populated with 0-
Ω
resistors and R21,R22 unpopulated
– GPIO22 and
GPIO23 are used as GPIO and go to the baseboard through EC1. The internal DC/DC
cannot be used.
• R18,R19 unpopulated and R21,R22 populated with 0-
Ω
resistors – Internal DC/DC can be
used to generate the 1.2-V VDD power rail. GPIO22 and GPIO23 are used as VFBSW and
VSW, respectively. The internal DC/DC can be used.
C19, C20, C21
These capacitors should be populated when the F28004x’s internal DC/DC capability is used.
C19 should be populated with a 2.2-µF capacitor. C20 and C21 should each be populated with a
10-µF capacitor.
R24, C28
R24 and C28 create an optional snubber circuit, which can be used if the DC/DC is used.
R36-R47,R49,R53, R60-R64, C41-C47,
and C48-C59
Optional RC input filter for all ADC/PGA inputs
C34-C40
PGA filter capacitor when PGA filtering is used
R55-R59
PGA-GND configuration resistors
R48,R50-R52,R54
These resistors control whether the negative input (PGAGND) for each PGA are grounded locally
or whether they should be grounded through pins on the HSEC connector (for use in Kelvin
grounding).
By default,
resistors R55-R59 are not populated and R48, R50-R52, R54 are populated
.
Because of this, all the PGAs are, by default, expected to be referenced to ground by the
baseboard. If, for example, R55 was populated and R48 was unpopulated, then PGA1’s
PGAGND would be grounded on the controlCARD.
Switches (default position in BOLD)
S1
Boot Mode Switch
Controls the boot options of the F28004x device. See the device data sheet for more information.
This switch is intentionally upside-down, so that logic 0 is down (the switch is closed) whereas
logic 1 is up (the switch is open). See
.
S2
GPIO10/GPIO35 Configuration Switches
In the up position – GPIO10 goes to pin 60 of the HSEC connector. If S4’s switch 1 is in the up
position, GPIO35 goes to pin 85 of the HSEC connector.
In the down position
– GPIO10 goes to pin 85 of the HSEC connector. If S4’s switch 1 is in the
up position, GPIO35 goes to pin 60 of the HSEC connector.
S3
GPIO08/GPIO37 Configuration Switches
In the up position
– GPIO08 goes to pin 87 of the HSEC connector. If S4’s switch 2 is in the up
position, GPIO37 goes to pin 58 of the HSEC connector.
In the down position – GPIO08 goes to pin 58 of the HSEC connector. If S4’s switch 2 is in the
up position, GPIO37 goes to pin 87 of the HSEC connector.
S4
JTAG/cJTAG Selection Switch
In the up position – 2-pin cJTAG mode is expected to be used. GPIO35 and GPIO37 go to the
baseboard based on the settings of S2 and S3, respectively.
In the down position
– 4-pin standard JTAG is expected to be used. GPIO35 and GPIO37 are
used to support JTAG functionality. The on-card xds100v2 emulator requires 4-pin JTAG to be
used.
