Texas Instruments PGA450Q1EVM, User Manual

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VPWR
5V
C1
0.1uF,0603,50V,10%,X7R
GND
5V
VPWR
GND GND
GND
F
P1
VPWR-IN
F
P3
GND
GND
FLZ8V2C
D2
VPROG_OTP (8V)
GND
JP1
VPWR:VOTP
VPWR
R1
6
2
0
,1
2
1
0
,1
/2
W
,5
%
VP_OTP_SOC
C3
1uF,0805,50V,10%,X7R
GND
C2
100uF,SMT,35V,20%,AL
JP2
VPWR
V_LIN
V_LIN
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
B260-13-F
A
2
C
1
D1
R2
DNP,0805,1/8W,5%
VP_OTP
POPULATE RESISTOR TO CONNECT V_OTP
PWR-IN
1
1
2
2
P2
GND VPWR-IN
TO THE SOLDERED DOWN PART
TPIC1021AQDRQ1
RXD
1
EN
2
NWAKE
3
TXD
4
GND
5
LIN
6
VSUP
7
INH
8
U1
LIN TxD GND
LIN RxD
GND
V_LIN
V_LIN
GND
LIN EN
FOOTPRINT OK 4/21/10
B
A
V
3
0
0
4
W
-7
-F
D3
R5
1.0k,0603,1/10W,5%
C5
220pF,0603,50V,10%,X7R
R4
1.0k,0603,1/10W,5%
C4
0
.1
u
F
,0
8
0
5
,5
0
V
,1
0
%
,X
7
R
R3
0
,0
6
0
3
,1
/1
0
W
,5
%
NWAKE
R6
0
,0
6
0
3
,1
/1
0
W
,5
%
GND
5V 5V
V_LIN LIN
GND
GND
LIN
PGA450Q1EVM Schematics and Layout Drawings
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22 SLDU007C – March 2012 – Revised November 2015
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PGA450Q1EVM User’s Guide
12 PGA450Q1EVM Schematics and Layout Drawings
Figure 18. Schematic, LIN
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Figure 19. Schematic, Power