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3
Hardware Description and Configuration
3.1
Power Supply Configuration
3.2
Analog Input
3.3
System Clock Configuration
Hardware Description and Configuration
This section provides hardware description and configuration information for the PCM4201EVM.
The PCM4201EVM requires three analog power supplies and one digital power supply for operation. The
analog supplies are connected at terminal block J2, while the digital supply is connected at terminal block
J6.
Analog supplies i15V and –15V DC for powering the input buffer circuit, as well as +5.0V DC for
powering the analog section of the PCM4201. All supplies should be rated for at least 500mA of output
current.
The digital supply re5.0V DC and should be rated for at least 500mA of output current. The +5.0V
supply is regulated to +3.3V DC by an onboard Texas Instruments REG1117 linear voltage regulator
(U10), which is used to power the digital section of the PCM4201 and the majority of the support logic
circuitry. The core logic and line driver sections of the AES3 transmitter (U7) utilize the +5.0V digital
supply directly.
An optional external VDD power supply is supported at terminal block J6. Jumper JMP4 is utilized to
select either the o3.3V voltage regulator (U10) or an external power source. Shorting pins 1 and
2 together using the supplied jumper block selects the o3.3V voltage regulator. Shorting pins 3
and 4 together will select the external supply (EXT VDD) on terminal block J6. Only one source may be
selected at any time.
The External VDD may be operated as low as +1.8V. However, the DIT4096 transmitter will only operate
at voltages down to +2.0V. Use the audio serial port interface at header J3 when operating VDD at
voltages lower than +2.0V.
The PCM4201EVM includes a Neutrik combo XLR connector (J1), which accepts either a 3-pin male XLR
or a 1/4-inch TRS phono plug. The analog input can accept up to a 18.5V
PP
differential input signal. This
signal is then attenuated by a factor of 3.7 by the input buffer circuit, which corresponds to the 5.0V
PP
full
scale differential input voltage for the PCM4201 analog input.
The input buffer circuit is comprised of an OPA2134 dual audio operational amplifier and associated
passive components. The input buffer provides active attenuation and low-pass filtering for the analog
input signal. The OPA2134 is biased to approxi2.5V, with the bias voltage being derived from the
+5V analog supply using a voltage divider.
The input buffer circuit may be configured to accept either dual or single supply op amps. Jumper JMP2
allows the –15V supply to be shorted to ground. The +15V may then be adjusted to the appropriate single
supply voltage for the op amp. When using a single supply op amp, it may be necessary to change the
values of the buffer feedback and input resistors in order to adjust the gain or attenuation to match the
maximum input/output voltage swing allowed by the single supply configuration.
The OSC1 and OSC2 elements of switch SW1 are utilized to select the system clock source for the
PCM4201EVM.
summarizes the available options. The onboard oscillators support 44.1kHz,
48kHz, 88.2kHz, and 96kHz sampling rates for Master mode audio serial port operation. Alternatively, the
external clock input (J4) may be used to supply the system clock from an external source, supporting
additional sampling rates.
For Slave mode operation, the system clock is input at the SCKI pin of the audio serial port header (J3).
6
SBAU108A – January 2005 – Revised February 2005
PCM4201EVM User's Guide
